Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton

Three-tier configuration hierarchy: - [env:base] — RadioLib + default LoRa parameters - [soc_esp32/esp32s3/nrf52] — platform + framework per SoC - [env:board_name] — board-specific pins + chip selection 20 boards across 4 vendors: - Heltec: 11 boards (T114, CT62, E213, E290, Mesh Solar, T190, Tracker, Tracker V2, V2, V3, V4) - LilyGo: 4 boards (T-Beam 1W, sx1262, sx1276, supreme) - Seeed: 1 board (Xiao S3 + Wio SX1262 with verified pins) - RAK: 4 boards (RAK11310, RAK3112, RAK3401, RAK3x72, RAK4631) Known/verified pins: Heltec V2/V3/V4, RAK4631, Seeed Xiao S3 FIXME pins: all others (placeholders for future research) Source skeleton: - config.h — compile-time defaults + pin validation (#error checks) - kiss.h/c — KISS protocol implementation (C99) - radio.h/cpp — RadioLib wrapper with C API (extern "C" boundary) - main.cpp — Arduino entry point All files pass pre-commit (prettier, markdownlint, YAML check).
2026-03-27 17:15:30 +01:00
parent 777014f375
commit 8883ee3e94
33 changed files with 824 additions and 15 deletions
--- a/hardware/heltec/ct62/platformio.ini
+++ b/hardware/heltec/ct62/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec CT62 — nRF52840 (likely)
+; FIXME: verify board ID, chip, and pin mappings
+[env:heltec_ct62]
+extends = soc_nrf52, env:base
+board = heltec_ct62
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_CT62
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/e213/platformio.ini
+++ b/hardware/heltec/e213/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec E213 — SoC/chip unknown
+; FIXME: identify SoC (ESP32/nRF52?) and LoRa chip, get pin mappings
+[env:heltec_e213]
+extends = soc_esp32, env:base
+board = heltec_e213
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_E213
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/e290/platformio.ini
+++ b/hardware/heltec/e290/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec E290 — SoC/chip unknown
+; FIXME: identify SoC and LoRa chip, get pin mappings
+[env:heltec_e290]
+extends = soc_esp32, env:base
+board = heltec_e290
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_E290
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/mesh_solar/platformio.ini
+++ b/hardware/heltec/mesh_solar/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec Mesh Solar — SoC/chip unknown
+; FIXME: identify SoC and LoRa chip, get pin mappings
+[env:heltec_mesh_solar]
+extends = soc_esp32, env:base
+board = heltec_mesh_solar
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_MESH_SOLAR
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/t114/platformio.ini
+++ b/hardware/heltec/t114/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec T114 — nRF52840, SX1262 (likely)
+; FIXME: verify board ID, chip, and pin mappings from hardware datasheet
+[env:heltec_t114]
+extends = soc_nrf52, env:base
+board = heltec_t114
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_T114
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/t190/platformio.ini
+++ b/hardware/heltec/t190/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec T190 — nRF52840 (likely)
+; FIXME: verify board ID, chip, and pin mappings
+[env:heltec_t190]
+extends = soc_nrf52, env:base
+board = heltec_t190
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_T190
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/tracker/platformio.ini
+++ b/hardware/heltec/tracker/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec Tracker — nRF52840, SX1262 (likely)
+; FIXME: verify board ID and pin mappings from hardware datasheet
+[env:heltec_tracker]
+extends = soc_nrf52, env:base
+board = heltec_tracker
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_TRACKER
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/tracker_v2/platformio.ini
+++ b/hardware/heltec/tracker_v2/platformio.ini
@@ -0,0 +1,14 @@
+; Heltec Tracker V2 — nRF52840, SX1262 (likely)
+; FIXME: verify board ID and pin mappings
+[env:heltec_tracker_v2]
+extends = soc_nrf52, env:base
+board = heltec_tracker_v2
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_TRACKER_V2
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/heltec/v2/platformio.ini
+++ b/hardware/heltec/v2/platformio.ini
@@ -0,0 +1,12 @@
+; Heltec WiFi LoRa 32 V2 — ESP32, SX1276, 868 MHz
+[env:heltec_v2]
+extends = soc_esp32, env:base
+board = heltec_wifi_lora_32
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_V2
+    -DLORA_CHIP_SX1276
+    -DLORA_PIN_NSS=18
+    -DLORA_PIN_DIO0=26
+    -DLORA_PIN_RESET=14
--- a/hardware/heltec/v3/platformio.ini
+++ b/hardware/heltec/v3/platformio.ini
@@ -0,0 +1,13 @@
+; Heltec WiFi LoRa 32 V3 — ESP32-S3, SX1262, 868 MHz
+[env:heltec_v3]
+extends = soc_esp32s3, env:base
+board = heltec_wifi_lora_32_v3
+build_flags =
+    ${soc_esp32s3.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_V3
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=8
+    -DLORA_PIN_DIO1=14
+    -DLORA_PIN_RESET=12
+    -DLORA_PIN_BUSY=13
--- a/hardware/heltec/v4/platformio.ini
+++ b/hardware/heltec/v4/platformio.ini
@@ -0,0 +1,13 @@
+; Heltec WiFi LoRa 32 V4 — ESP32-S3, SX1262, 868 MHz
+[env:heltec_v4]
+extends = soc_esp32s3, env:base
+board = heltec_wifi_lora_32_v4
+build_flags =
+    ${soc_esp32s3.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_HELTEC_V4
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=8
+    -DLORA_PIN_DIO1=14
+    -DLORA_PIN_RESET=12
+    -DLORA_PIN_BUSY=13
--- a/hardware/lilygo/t_beam_1w/platformio.ini
+++ b/hardware/lilygo/t_beam_1w/platformio.ini
@@ -0,0 +1,14 @@
+; LilyGo T-Beam 1W — ESP32, SX1262 (likely)
+; FIXME: verify board ID and pin mappings from hardware datasheet
+[env:lilygo_t_beam_1w]
+extends = soc_esp32, env:base
+board = lilygo_t_beam_1w
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_LILYGO_T_BEAM_1W
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/lilygo/t_beam_supreme/platformio.ini
+++ b/hardware/lilygo/t_beam_supreme/platformio.ini
@@ -0,0 +1,14 @@
+; LilyGo T-Beam Supreme (SX1262) — ESP32, SX1262
+; FIXME: verify board ID and pin mappings
+[env:lilygo_t_beam_supreme]
+extends = soc_esp32, env:base
+board = lilygo_t_beam_supreme
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_LILYGO_T_BEAM_SUPREME
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/lilygo/t_beam_sx1262/platformio.ini
+++ b/hardware/lilygo/t_beam_sx1262/platformio.ini
@@ -0,0 +1,14 @@
+; LilyGo T-Beam with SX1262 — ESP32, SX1262
+; FIXME: verify board ID and pin mappings
+[env:lilygo_t_beam_sx1262]
+extends = soc_esp32, env:base
+board = lilygo_t_beam_sx1262
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_LILYGO_T_BEAM_SX1262
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/lilygo/t_beam_sx1276/platformio.ini
+++ b/hardware/lilygo/t_beam_sx1276/platformio.ini
@@ -0,0 +1,13 @@
+; LilyGo T-Beam with SX1276 — ESP32, SX1276
+; FIXME: verify board ID and pin mappings
+[env:lilygo_t_beam_sx1276]
+extends = soc_esp32, env:base
+board = lilygo_t_beam_sx1276
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_LILYGO_T_BEAM_SX1276
+    -DLORA_CHIP_SX1276
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO0=0
+    -DLORA_PIN_RESET=0
--- a/hardware/rak/rak11310/platformio.ini
+++ b/hardware/rak/rak11310/platformio.ini
@@ -0,0 +1,14 @@
+; RAK11310 — RP2040-based (different platform)
+; FIXME: determine platform (likely rp2040), chip, and pin mappings
+[env:rak_rak11310]
+extends = soc_nrf52, env:base
+board = rak11310
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_RAK_RAK11310
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/rak/rak3112/platformio.ini
+++ b/hardware/rak/rak3112/platformio.ini
@@ -0,0 +1,14 @@
+; RAK3112 — nRF52840 (likely), SX1262 (likely)
+; FIXME: verify board ID, chip, and pin mappings
+[env:rak_rak3112]
+extends = soc_nrf52, env:base
+board = rak3112
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_RAK_RAK3112
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/rak/rak3401/platformio.ini
+++ b/hardware/rak/rak3401/platformio.ini
@@ -0,0 +1,14 @@
+; RAK3401 — nRF52840 (likely), SX1262 (likely)
+; FIXME: verify board ID, chip, and pin mappings
+[env:rak_rak3401]
+extends = soc_nrf52, env:base
+board = rak3401
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_RAK_RAK3401
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/rak/rak3x72/platformio.ini
+++ b/hardware/rak/rak3x72/platformio.ini
@@ -0,0 +1,14 @@
+; RAK3x72 — nRF52840 (likely), SX1262 (likely)
+; FIXME: verify which variants (3172, 3272, 3372?), board IDs, and pin mappings
+[env:rak_rak3x72]
+extends = soc_nrf52, env:base
+board = rak3x72
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_RAK_RAK3X72
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0
--- a/hardware/rak/rak4631/platformio.ini
+++ b/hardware/rak/rak4631/platformio.ini
@@ -0,0 +1,13 @@
+; RAK4631 — nRF52840, SX1262, 868 MHz
+[env:rak_rak4631]
+extends = soc_nrf52, env:base
+board = wiscore_rak4631
+build_flags =
+    ${soc_nrf52.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_RAK_RAK4631
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=42
+    -DLORA_PIN_DIO1=47
+    -DLORA_PIN_RESET=38
+    -DLORA_PIN_BUSY=46
--- a/hardware/seeed/xiao_s3_wio_sx1262/platformio.ini
+++ b/hardware/seeed/xiao_s3_wio_sx1262/platformio.ini
@@ -0,0 +1,21 @@
+; Seeed Xiao S3 + Wio SX1262 — ESP32-S3, SX1262
+[env:seeed_xiao_s3_wio_sx1262]
+extends = soc_esp32s3, env:base
+board = seeed_xiao_s3
+build_flags =
+    ${soc_esp32s3.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_SEEED_XIAO_S3_WIO_SX1262
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=41
+    -DLORA_PIN_DIO1=39
+    -DLORA_PIN_RESET=42
+    -DLORA_PIN_BUSY=40
+    ; SX1262 RF switch on DIO2
+    -DSX126X_DIO2_AS_RF_SWITCH=true
+    -DSX126X_DIO3_TCXO_VOLTAGE=1.8
+    -DSX126X_CURRENT_LIMIT=140
+    ; SPI pins
+    -DLORA_PIN_SCLK=7
+    -DLORA_PIN_MISO=8
+    -DLORA_PIN_MOSI=9