Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton

Three-tier configuration hierarchy:
- [env:base] — RadioLib + default LoRa parameters
- [soc_esp32/esp32s3/nrf52] — platform + framework per SoC
- [env:board_name] — board-specific pins + chip selection

20 boards across 4 vendors:
- Heltec: 11 boards (T114, CT62, E213, E290, Mesh Solar, T190, Tracker,
  Tracker V2, V2, V3, V4)
- LilyGo: 4 boards (T-Beam 1W, sx1262, sx1276, supreme)
- Seeed: 1 board (Xiao S3 + Wio SX1262 with verified pins)
- RAK: 4 boards (RAK11310, RAK3112, RAK3401, RAK3x72, RAK4631)

Known/verified pins: Heltec V2/V3/V4, RAK4631, Seeed Xiao S3
FIXME pins: all others (placeholders for future research)

Source skeleton:
- config.h — compile-time defaults + pin validation (#error checks)
- kiss.h/c — KISS protocol implementation (C99)
- radio.h/cpp — RadioLib wrapper with C API (extern "C" boundary)
- main.cpp — Arduino entry point

All files pass pre-commit (prettier, markdownlint, YAML check).

hardware/lilygo/t_beam_supreme/platformio.ini

@@ -0,0 +1,14 @@
+; LilyGo T-Beam Supreme (SX1262) — ESP32, SX1262
+; FIXME: verify board ID and pin mappings
+[env:lilygo_t_beam_supreme]
+extends = soc_esp32, env:base
+board = lilygo_t_beam_supreme
+build_flags =
+    ${soc_esp32.build_flags}
+    ${env:base.build_flags}
+    -DBOARD_LILYGO_T_BEAM_SUPREME
+    -DLORA_CHIP_SX1262
+    -DLORA_PIN_NSS=0
+    -DLORA_PIN_DIO1=0
+    -DLORA_PIN_RESET=0
+    -DLORA_PIN_BUSY=0