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b12ad6fba6
Use build matrix
main
Wijnand Modderman-Lenstra
2026-03-30 09:40:35 +02:00
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cb02cf229d
Replace matrix strategy with explicit parallel build jobs
Maze X
2026-03-27 18:09:28 +01:00
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fdd1802bd5
Restructure CI pipeline for proper sequencing and parallelization
Maze X
2026-03-27 18:08:42 +01:00
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bd2f990754
Add firmware artifact collection and Gitea package publishing
Maze X
2026-03-27 18:06:28 +01:00
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5bdf28b83c
Add custom board definition for Heltec WiFi LoRa 32 V3
Maze X
2026-03-27 18:05:21 +01:00
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a72e2f01ff
Update CI pipeline: enforce lint → test → build order and reduce targets
Maze X
2026-03-27 18:02:27 +01:00
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f7bd449e6f
Add Gitea Actions CI/CD infrastructure with build matrix
Maze X
2026-03-27 17:53:08 +01:00
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3baf7df0d1
Apply clang-format to source files and fix linter config
Maze X
2026-03-27 17:48:39 +01:00
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20b3aae1e3
Add Python KISS client and integration test framework
Maze X
2026-03-27 17:46:33 +01:00
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2924c8e792
Add clang-format and clang-tidy to pre-commit hooks
Maze X
2026-03-27 17:41:27 +01:00
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cb14666710
Add unit test framework and test stubs
Maze X
2026-03-27 17:40:49 +01:00
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138f897090
Change default syncword from 0x34 to 0x12
Maze X
2026-03-27 17:39:12 +01:00
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add91bb47b
Implement Port 2 (config commands) handler in main.cpp
Maze X
2026-03-27 17:38:18 +01:00
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9f6c115001
Implement SX126X SPI and chip configuration for PoC
Maze X
2026-03-27 17:33:23 +01:00
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c67b2e6b75
Rename GPIO macros: PIN_<foo>_* → <foo>_PIN_*
Maze X
2026-03-27 17:18:26 +01:00
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2dd1e830ba
Add comprehensive pin definitions for Heltec V3 (renamed to SOC_PIN_*/GPS_PIN_*)
Maze X
2026-03-27 17:17:09 +01:00
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8883ee3e94
Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton
Maze X
2026-03-27 17:15:30 +01:00
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777014f375
Initial setup
Maze X
2026-03-27 16:46:56 +01:00