/*
 * Generated by gen_defines.py
 *
 * DTS input file:
 *   /Volumes/External/Work/radio/loramodem/build/zephyr/zephyr.dts.pre
 *
 * Directories with bindings:
 *   /Volumes/External/Work/radio/loramodem/dts/bindings, $ZEPHYR_BASE/dts/bindings
 *
 * Node dependency ordering (ordinal and path):
 *   0   /
 *   1   /aliases
 *   2   /chosen
 *   3   /connector
 *   4   /esp32_bt_hci
 *   5   /wifi
 *   6   /cpus
 *   7   /cpus/power-states
 *   8   /cpus/power-states/deep_sleep
 *   9   /cpus/power-states/light_sleep
 *   10  /cpus/cpu@0
 *   11  /cpus/cpu@1
 *   12  /soc
 *   13  /soc/gpio
 *   14  /soc/interrupt-controller@600c2000
 *   15  /soc/gpio/gpio@60004000
 *   16  /leds
 *   17  /leds/led_0
 *   18  /pin-controller
 *   19  /pin-controller/i2c0_default
 *   20  /pin-controller/i2c0_default/group1
 *   21  /pin-controller/i2c1_default
 *   22  /pin-controller/i2c1_default/group1
 *   23  /pin-controller/lcd_cam_default
 *   24  /pin-controller/lcd_cam_default/group1
 *   25  /pin-controller/lcd_cam_default/group2
 *   26  /pin-controller/spim2_default
 *   27  /pin-controller/spim2_default/group1
 *   28  /pin-controller/spim2_default/group2
 *   29  /pin-controller/twai_default
 *   30  /pin-controller/twai_default/group1
 *   31  /pin-controller/uart0_default
 *   32  /pin-controller/uart0_default/group1
 *   33  /pin-controller/uart0_default/group2
 *   34  /clock
 *   35  /soc/adc@60040000
 *   36  /soc/adc@60040004
 *   37  /soc/aes@6003a000
 *   38  /soc/can@6002b000
 *   39  /soc/coretemp@60008800
 *   40  /soc/i2c@60013000
 *   41  /soc/i2c@60027000
 *   42  /soc/dma@6003f000
 *   43  /soc/i2s@6000f000
 *   44  /soc/i2s@6002d000
 *   45  /soc/memory@3fce5000
 *   46  /soc/ipm@3fce9400
 *   47  /soc/ledc@60019000
 *   48  /soc/mbox@3fce9408
 *   49  /soc/mcpwm@6001e000
 *   50  /soc/mcpwm@6002c000
 *   51  /soc/memory@3fc88000
 *   52  /soc/memory@3fce5400
 *   53  /soc/memory@3fcf0000
 *   54  /soc/memory@40370000
 *   55  /soc/memory@42000000
 *   56  /soc/memory@50000000
 *   57  /soc/memory@600fe000
 *   58  /soc/pcnt@60017000
 *   59  /soc/rtc_timer@60008004
 *   60  /soc/sha@6003b000
 *   61  /soc/spi@60025000
 *   62  /soc/touch@6000885c
 *   63  /soc/trng@6003507c
 *   64  /soc/uart@60000000
 *   65  /soc/uart@60010000
 *   66  /soc/uart@6002e000
 *   67  /soc/uart@60038000
 *   68  /soc/usb_otg@60080000
 *   69  /soc/watchdog@6001f048
 *   70  /soc/watchdog@60020048
 *   71  /soc/xt_wdt@60021004
 *   72  /soc/counter@6001f000
 *   73  /soc/counter@6001f000/counter
 *   74  /soc/counter@6001f024
 *   75  /soc/counter@6001f024/counter
 *   76  /soc/counter@60020000
 *   77  /soc/counter@60020000/counter
 *   78  /soc/counter@60020024
 *   79  /soc/counter@60020024/counter
 *   80  /soc/flash-controller@60002000
 *   81  /soc/flash-controller@60002000/flash@0
 *   82  /soc/flash-controller@60002000/flash@0/partitions
 *   83  /soc/flash-controller@60002000/flash@0/partitions/partition@0
 *   84  /soc/flash-controller@60002000/flash@0/partitions/partition@10000
 *   85  /soc/flash-controller@60002000/flash@0/partitions/partition@20000
 *   86  /soc/flash-controller@60002000/flash@0/partitions/partition@170000
 *   87  /soc/flash-controller@60002000/flash@0/partitions/partition@2c0000
 *   88  /soc/flash-controller@60002000/flash@0/partitions/partition@330000
 *   89  /soc/flash-controller@60002000/flash@0/partitions/partition@3a0000
 *   90  /soc/flash-controller@60002000/flash@0/partitions/partition@3a8000
 *   91  /soc/flash-controller@60002000/flash@0/partitions/partition@3b0000
 *   92  /soc/flash-controller@60002000/flash@0/partitions/partition@3e0000
 *   93  /soc/flash-controller@60002000/flash@0/partitions/partition@3ff000
 *   94  /soc/gpio/gpio@60004800
 *   95  /soc/lcd_cam@60041000
 *   96  /soc/lcd_cam@60041000/lcd_cam_disp
 *   97  /soc/lcd_cam@60041000/lcd_cam_dvp
 *   98  /soc/memory@3c000000
 *   99  /soc/memory@3c000000/psram0
 *   100 /soc/sdhc@60028000
 *   101 /soc/sdhc@60028000/sdhc@0
 *   102 /soc/sdhc@60028000/sdhc@1
 *   103 /soc/spi@60024000
 *   104 /soc/spi@60024000/lora@0
 *
 * Definitions derived from these nodes in dependency order are next,
 * followed by /chosen nodes.
 */

/* Used to remove brackets from around a single argument */
#define DT_DEBRACKET_INTERNAL(...) __VA_ARGS__

/*
 * Devicetree node: /
 *
 * Node identifier: DT_N
 */

/* Node's full path: */
#define DT_N_PATH "/"

/* Node's name with unit-address: */
#define DT_N_FULL_NAME "/"
#define DT_N_FULL_NAME_UNQUOTED /
#define DT_N_FULL_NAME_TOKEN _
#define DT_N_FULL_NAME_UPPER_TOKEN _

/* Helpers for dealing with node labels: */
#define DT_N_NODELABEL_NUM 0
#define DT_N_FOREACH_NODELABEL(fn) 
#define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_FOREACH_ANCESTOR(fn) 

/* Helper macros for child nodes of this node. */
#define DT_N_CHILD_NUM 10
#define DT_N_CHILD_NUM_STATUS_OKAY 10
#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_wifi) fn(DT_N_S_esp32_bt_hci) fn(DT_N_S_pin_controller) fn(DT_N_S_clock) fn(DT_N_S_connector) fn(DT_N_S_leds)
#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_wifi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_esp32_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clock) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds)
#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_wifi, __VA_ARGS__) fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_clock, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_wifi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clock, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_wifi) fn(DT_N_S_esp32_bt_hci) fn(DT_N_S_pin_controller) fn(DT_N_S_clock) fn(DT_N_S_connector) fn(DT_N_S_leds)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_wifi) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_esp32_bt_hci) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clock) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_wifi, __VA_ARGS__) fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_clock, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_wifi, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clock, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__)

/* Node's hash: */
#define DT_N_HASH il7asoJjJEMhngUeSt4tHVu8Zxx4EFG_FDeJfL3_oPE

/* Node's dependency ordinal: */
#define DT_N_ORD 0
#define DT_N_ORD_STR_SORTABLE 00000

/* Ordinals for what this node depends on directly: */
#define DT_N_REQUIRES_ORDS /* nothing */

/* Ordinals for what depends directly on this node: */
#define DT_N_SUPPORTS_ORDS \
	1, /* /aliases */ \
	2, /* /chosen */ \
	3, /* /connector */ \
	4, /* /esp32_bt_hci */ \
	5, /* /wifi */ \
	6, /* /cpus */ \
	12, /* /soc */ \
	16, /* /leds */ \
	18, /* /pin-controller */ \
	34, /* /clock */

/* Existence and alternate IDs: */
#define DT_N_EXISTS 1
#define DT_N_INST_0_seeed_xiao_esp32s3 DT_N

/* Macros for properties that are special in the specification: */
#define DT_N_REG_NUM 0
#define DT_N_FOREACH_REG(fn) 
#define DT_N_FOREACH_REG_SEP(fn, sep) 
#define DT_N_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_RANGES_NUM 0
#define DT_N_FOREACH_RANGE(fn) 
#define DT_N_IRQ_NUM 0
#define DT_N_IRQ_LEVEL 0
#define DT_N_COMPAT_MATCHES_seeed_xiao_esp32s3 1
#define DT_N_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_COMPAT_VENDOR_IDX_0 "Seeed Technology Co., Ltd"
#define DT_N_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_COMPAT_MODEL_IDX_0 "xiao-esp32s3"
#define DT_N_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_P_compatible {"seeed,xiao-esp32s3"}
#define DT_N_P_compatible_IDX_0_EXISTS 1
#define DT_N_P_compatible_IDX_0 "seeed,xiao-esp32s3"
#define DT_N_P_compatible_IDX_0_STRING_UNQUOTED seeed,xiao-esp32s3
#define DT_N_P_compatible_IDX_0_STRING_TOKEN seeed_xiao_esp32s3
#define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN SEEED_XIAO_ESP32S3
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N, compatible, 0, __VA_ARGS__)
#define DT_N_P_compatible_LEN 1
#define DT_N_P_compatible_EXISTS 1

/*
 * Devicetree node: /aliases
 *
 * Node identifier: DT_N_S_aliases
 */

/* Node's full path: */
#define DT_N_S_aliases_PATH "/aliases"

/* Node's name with unit-address: */
#define DT_N_S_aliases_FULL_NAME "aliases"
#define DT_N_S_aliases_FULL_NAME_UNQUOTED aliases
#define DT_N_S_aliases_FULL_NAME_TOKEN aliases
#define DT_N_S_aliases_FULL_NAME_UPPER_TOKEN ALIASES

/* Node parent (/) identifier: */
#define DT_N_S_aliases_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_aliases_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_aliases_NODELABEL_NUM 0
#define DT_N_S_aliases_FOREACH_NODELABEL(fn) 
#define DT_N_S_aliases_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_aliases_CHILD_NUM 0
#define DT_N_S_aliases_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_aliases_FOREACH_CHILD(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_aliases_HASH QavYY6yplHKhLPRKsRzaLCGlR0CWZ0JUNJakcBCfDXA

/* Node's dependency ordinal: */
#define DT_N_S_aliases_ORD 1
#define DT_N_S_aliases_ORD_STR_SORTABLE 00001

/* Ordinals for what this node depends on directly: */
#define DT_N_S_aliases_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_aliases_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_aliases_REG_NUM 0
#define DT_N_S_aliases_FOREACH_REG(fn) 
#define DT_N_S_aliases_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_aliases_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_aliases_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_aliases_RANGES_NUM 0
#define DT_N_S_aliases_FOREACH_RANGE(fn) 
#define DT_N_S_aliases_IRQ_NUM 0
#define DT_N_S_aliases_IRQ_LEVEL 0
#define DT_N_S_aliases_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_aliases_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /chosen
 *
 * Node identifier: DT_N_S_chosen
 */

/* Node's full path: */
#define DT_N_S_chosen_PATH "/chosen"

/* Node's name with unit-address: */
#define DT_N_S_chosen_FULL_NAME "chosen"
#define DT_N_S_chosen_FULL_NAME_UNQUOTED chosen
#define DT_N_S_chosen_FULL_NAME_TOKEN chosen
#define DT_N_S_chosen_FULL_NAME_UPPER_TOKEN CHOSEN

/* Node parent (/) identifier: */
#define DT_N_S_chosen_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_chosen_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_chosen_NODELABEL_NUM 0
#define DT_N_S_chosen_FOREACH_NODELABEL(fn) 
#define DT_N_S_chosen_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_chosen_CHILD_NUM 0
#define DT_N_S_chosen_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_chosen_FOREACH_CHILD(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_chosen_HASH qNExeeLInzqaWpm1KroyYDk4lRIxVO2ig78mq_hOnA8

/* Node's dependency ordinal: */
#define DT_N_S_chosen_ORD 2
#define DT_N_S_chosen_ORD_STR_SORTABLE 00002

/* Ordinals for what this node depends on directly: */
#define DT_N_S_chosen_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_chosen_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_chosen_REG_NUM 0
#define DT_N_S_chosen_FOREACH_REG(fn) 
#define DT_N_S_chosen_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_chosen_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_chosen_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_chosen_RANGES_NUM 0
#define DT_N_S_chosen_FOREACH_RANGE(fn) 
#define DT_N_S_chosen_IRQ_NUM 0
#define DT_N_S_chosen_IRQ_LEVEL 0
#define DT_N_S_chosen_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_chosen_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /connector
 *
 * Node identifier: DT_N_S_connector
 *
 * Binding (compatible = seeed,xiao-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/seeed,xiao-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_connector_PATH "/connector"

/* Node's name with unit-address: */
#define DT_N_S_connector_FULL_NAME "connector"
#define DT_N_S_connector_FULL_NAME_UNQUOTED connector
#define DT_N_S_connector_FULL_NAME_TOKEN connector
#define DT_N_S_connector_FULL_NAME_UPPER_TOKEN CONNECTOR

/* Node parent (/) identifier: */
#define DT_N_S_connector_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_connector_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_connector_NODELABEL_NUM 1
#define DT_N_S_connector_FOREACH_NODELABEL(fn) fn(xiao_d)
#define DT_N_S_connector_FOREACH_NODELABEL_VARGS(fn, ...) fn(xiao_d, __VA_ARGS__)
#define DT_N_S_connector_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_connector_CHILD_NUM 0
#define DT_N_S_connector_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_connector_FOREACH_CHILD(fn) 
#define DT_N_S_connector_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_connector_HASH 1hNYiTso4N65bku_L_0pzRcHL_5NCz8DqiXd1i5KK7Q

/* Node's dependency ordinal: */
#define DT_N_S_connector_ORD 3
#define DT_N_S_connector_ORD_STR_SORTABLE 00003

/* Ordinals for what this node depends on directly: */
#define DT_N_S_connector_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_connector_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_connector_EXISTS 1
#define DT_N_INST_0_seeed_xiao_gpio DT_N_S_connector
#define DT_N_NODELABEL_xiao_d       DT_N_S_connector

/* Macros for properties that are special in the specification: */
#define DT_N_S_connector_REG_NUM 0
#define DT_N_S_connector_FOREACH_REG(fn) 
#define DT_N_S_connector_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_connector_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_connector_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_connector_RANGES_NUM 0
#define DT_N_S_connector_FOREACH_RANGE(fn) 
#define DT_N_S_connector_IRQ_NUM 0
#define DT_N_S_connector_IRQ_LEVEL 0
#define DT_N_S_connector_COMPAT_MATCHES_seeed_xiao_gpio 1
#define DT_N_S_connector_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_connector_COMPAT_VENDOR_IDX_0 "Seeed Technology Co., Ltd"
#define DT_N_S_connector_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_connector_COMPAT_MODEL_IDX_0 "xiao-gpio"
#define DT_N_S_connector_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_connector_PINCTRL_NUM 0

/* Map properties: */
#define DT_N_S_connector_P_gpio_map_LEN 11
#define DT_N_S_connector_P_gpio_map_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_0 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_2_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_0 3
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_3_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_0 4
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_4_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_0 5
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_5_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_0 6
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT DT_N_S_soc_S_gpio_S_gpio_60004800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_0 11
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_6_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT DT_N_S_soc_S_gpio_S_gpio_60004800
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_0 12
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_7_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_0 7
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_8_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_0 8
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_9_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_0 10
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_ADDRESS_LEN 0
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_LEN 2
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_0 9
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_MAP_ENTRY_10_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY(fn) fn(DT_N_S_connector, gpio_map, 0) \
	fn(DT_N_S_connector, gpio_map, 1) \
	fn(DT_N_S_connector, gpio_map, 2) \
	fn(DT_N_S_connector, gpio_map, 3) \
	fn(DT_N_S_connector, gpio_map, 4) \
	fn(DT_N_S_connector, gpio_map, 5) \
	fn(DT_N_S_connector, gpio_map, 6) \
	fn(DT_N_S_connector, gpio_map, 7) \
	fn(DT_N_S_connector, gpio_map, 8) \
	fn(DT_N_S_connector, gpio_map, 9) \
	fn(DT_N_S_connector, gpio_map, 10)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP(fn, sep) fn(DT_N_S_connector, gpio_map, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_FOREACH_MAP_ENTRY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map, 10, __VA_ARGS__)

/* Generic property macros: */
#define DT_N_S_connector_P_gpio_map_mask {4294967295 /* 0xffffffff */, 4294967232 /* 0xffffffc0 */}
#define DT_N_S_connector_P_gpio_map_mask_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_0 4294967295
#define DT_N_S_connector_P_gpio_map_mask_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_mask_IDX_1 4294967232
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_mask, 0) \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_mask, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_mask, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_mask, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_mask_LEN 2
#define DT_N_S_connector_P_gpio_map_mask_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru {0 /* 0x0 */, 63 /* 0x3f */}
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_0 0
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1_EXISTS 1
#define DT_N_S_connector_P_gpio_map_pass_thru_IDX_1 63
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, gpio_map_pass_thru, 0) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, gpio_map_pass_thru, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, gpio_map_pass_thru, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_connector, gpio_map_pass_thru, 1, __VA_ARGS__)
#define DT_N_S_connector_P_gpio_map_pass_thru_LEN 2
#define DT_N_S_connector_P_gpio_map_pass_thru_EXISTS 1
#define DT_N_S_connector_P_compatible {"seeed,xiao-gpio"}
#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_connector_P_compatible_IDX_0 "seeed,xiao-gpio"
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED seeed,xiao-gpio
#define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN seeed_xiao_gpio
#define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN SEEED_XIAO_GPIO
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__)
#define DT_N_S_connector_P_compatible_LEN 1
#define DT_N_S_connector_P_compatible_EXISTS 1
#define DT_N_S_connector_P_zephyr_deferred_init 0
#define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_connector_P_wakeup_source 0
#define DT_N_S_connector_P_wakeup_source_EXISTS 1
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /esp32_bt_hci
 *
 * Node identifier: DT_N_S_esp32_bt_hci
 *
 * Binding (compatible = espressif,esp32-bt-hci):
 *   $ZEPHYR_BASE/dts/bindings/bluetooth/espressif,esp32-bt-hci.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_esp32_bt_hci_PATH "/esp32_bt_hci"

/* Node's name with unit-address: */
#define DT_N_S_esp32_bt_hci_FULL_NAME "esp32_bt_hci"
#define DT_N_S_esp32_bt_hci_FULL_NAME_UNQUOTED esp32_bt_hci
#define DT_N_S_esp32_bt_hci_FULL_NAME_TOKEN esp32_bt_hci
#define DT_N_S_esp32_bt_hci_FULL_NAME_UPPER_TOKEN ESP32_BT_HCI

/* Node parent (/) identifier: */
#define DT_N_S_esp32_bt_hci_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_esp32_bt_hci_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_esp32_bt_hci_NODELABEL_NUM 1
#define DT_N_S_esp32_bt_hci_FOREACH_NODELABEL(fn) fn(esp32_bt_hci)
#define DT_N_S_esp32_bt_hci_FOREACH_NODELABEL_VARGS(fn, ...) fn(esp32_bt_hci, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_esp32_bt_hci_CHILD_NUM 0
#define DT_N_S_esp32_bt_hci_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD(fn) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_esp32_bt_hci_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_esp32_bt_hci_HASH WzQFLnWOli81_h6U7zBvNN_8VSeDs53nERgPVwn7L3U

/* Node's dependency ordinal: */
#define DT_N_S_esp32_bt_hci_ORD 4
#define DT_N_S_esp32_bt_hci_ORD_STR_SORTABLE 00004

/* Ordinals for what this node depends on directly: */
#define DT_N_S_esp32_bt_hci_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_esp32_bt_hci_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_esp32_bt_hci_EXISTS 1
#define DT_N_INST_0_espressif_esp32_bt_hci DT_N_S_esp32_bt_hci
#define DT_N_NODELABEL_esp32_bt_hci        DT_N_S_esp32_bt_hci

/* Macros for properties that are special in the specification: */
#define DT_N_S_esp32_bt_hci_REG_NUM 0
#define DT_N_S_esp32_bt_hci_FOREACH_REG(fn) 
#define DT_N_S_esp32_bt_hci_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_esp32_bt_hci_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_esp32_bt_hci_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_esp32_bt_hci_RANGES_NUM 0
#define DT_N_S_esp32_bt_hci_FOREACH_RANGE(fn) 
#define DT_N_S_esp32_bt_hci_IRQ_NUM 0
#define DT_N_S_esp32_bt_hci_IRQ_LEVEL 0
#define DT_N_S_esp32_bt_hci_COMPAT_MATCHES_espressif_esp32_bt_hci 1
#define DT_N_S_esp32_bt_hci_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_esp32_bt_hci_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_COMPAT_MODEL_IDX_0 "esp32-bt-hci"
#define DT_N_S_esp32_bt_hci_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_esp32_bt_hci_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_esp32_bt_hci_P_bt_hci_name "BT ESP32"
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_STRING_UNQUOTED BT ESP32
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_STRING_TOKEN BT_ESP32
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_STRING_UPPER_TOKEN BT_ESP32
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_IDX_0 "BT ESP32"
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_esp32_bt_hci, bt_hci_name, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_esp32_bt_hci, bt_hci_name, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_name, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_LEN 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_name_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus "ipc"
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_STRING_UNQUOTED ipc
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_STRING_TOKEN ipc
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_STRING_UPPER_TOKEN IPC
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_IDX_0 "ipc"
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_IDX_0_ENUM_IDX 11
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_IDX_0_ENUM_VAL_ipc_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_ENUM_VAL_ipc_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_esp32_bt_hci, bt_hci_bus, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_esp32_bt_hci, bt_hci_bus, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_bus, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_LEN 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_bus_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks {"no-auto-dle"}
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_ENUM_IDX 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_ENUM_VAL_no_auto_dle_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_ENUM_VAL_no_auto_dle_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0 "no-auto-dle"
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_STRING_UNQUOTED no-auto-dle
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_STRING_TOKEN no_auto_dle
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_IDX_0_STRING_UPPER_TOKEN NO_AUTO_DLE
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_esp32_bt_hci, bt_hci_quirks, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_esp32_bt_hci, bt_hci_quirks, 0)
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_esp32_bt_hci, bt_hci_quirks, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_LEN 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_quirks_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_vs_ext 1
#define DT_N_S_esp32_bt_hci_P_bt_hci_vs_ext_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_status "okay"
#define DT_N_S_esp32_bt_hci_P_status_STRING_UNQUOTED okay
#define DT_N_S_esp32_bt_hci_P_status_STRING_TOKEN okay
#define DT_N_S_esp32_bt_hci_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_esp32_bt_hci_P_status_IDX_0 "okay"
#define DT_N_S_esp32_bt_hci_P_status_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_esp32_bt_hci_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_esp32_bt_hci, status, 0)
#define DT_N_S_esp32_bt_hci_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_esp32_bt_hci, status, 0)
#define DT_N_S_esp32_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_esp32_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_esp32_bt_hci, status, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_status_LEN 1
#define DT_N_S_esp32_bt_hci_P_status_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_compatible {"espressif,esp32-bt-hci"}
#define DT_N_S_esp32_bt_hci_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_compatible_IDX_0 "espressif,esp32-bt-hci"
#define DT_N_S_esp32_bt_hci_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-bt-hci
#define DT_N_S_esp32_bt_hci_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_bt_hci
#define DT_N_S_esp32_bt_hci_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_BT_HCI
#define DT_N_S_esp32_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_esp32_bt_hci, compatible, 0)
#define DT_N_S_esp32_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_esp32_bt_hci, compatible, 0)
#define DT_N_S_esp32_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_esp32_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_esp32_bt_hci, compatible, 0, __VA_ARGS__)
#define DT_N_S_esp32_bt_hci_P_compatible_LEN 1
#define DT_N_S_esp32_bt_hci_P_compatible_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_zephyr_deferred_init 0
#define DT_N_S_esp32_bt_hci_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_wakeup_source 0
#define DT_N_S_esp32_bt_hci_P_wakeup_source_EXISTS 1
#define DT_N_S_esp32_bt_hci_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_esp32_bt_hci_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /wifi
 *
 * Node identifier: DT_N_S_wifi
 *
 * Binding (compatible = espressif,esp32-wifi):
 *   $ZEPHYR_BASE/dts/bindings/wifi/espressif,esp32-wifi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_wifi_PATH "/wifi"

/* Node's name with unit-address: */
#define DT_N_S_wifi_FULL_NAME "wifi"
#define DT_N_S_wifi_FULL_NAME_UNQUOTED wifi
#define DT_N_S_wifi_FULL_NAME_TOKEN wifi
#define DT_N_S_wifi_FULL_NAME_UPPER_TOKEN WIFI

/* Node parent (/) identifier: */
#define DT_N_S_wifi_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_wifi_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_wifi_NODELABEL_NUM 1
#define DT_N_S_wifi_FOREACH_NODELABEL(fn) fn(wifi)
#define DT_N_S_wifi_FOREACH_NODELABEL_VARGS(fn, ...) fn(wifi, __VA_ARGS__)
#define DT_N_S_wifi_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_wifi_CHILD_NUM 0
#define DT_N_S_wifi_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_wifi_FOREACH_CHILD(fn) 
#define DT_N_S_wifi_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_wifi_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_wifi_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_wifi_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_wifi_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_wifi_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_wifi_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_wifi_HASH rr0vN_kubTtnlX0gdAC83Y08AGdecB14WmkrlyFB8RE

/* Node's dependency ordinal: */
#define DT_N_S_wifi_ORD 5
#define DT_N_S_wifi_ORD_STR_SORTABLE 00005

/* Ordinals for what this node depends on directly: */
#define DT_N_S_wifi_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_wifi_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_wifi_EXISTS 1
#define DT_N_INST_0_espressif_esp32_wifi DT_N_S_wifi
#define DT_N_NODELABEL_wifi              DT_N_S_wifi

/* Macros for properties that are special in the specification: */
#define DT_N_S_wifi_REG_NUM 0
#define DT_N_S_wifi_FOREACH_REG(fn) 
#define DT_N_S_wifi_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_wifi_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_wifi_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_wifi_RANGES_NUM 0
#define DT_N_S_wifi_FOREACH_RANGE(fn) 
#define DT_N_S_wifi_IRQ_NUM 0
#define DT_N_S_wifi_IRQ_LEVEL 0
#define DT_N_S_wifi_COMPAT_MATCHES_espressif_esp32_wifi 1
#define DT_N_S_wifi_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_wifi_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_wifi_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_wifi_COMPAT_MODEL_IDX_0 "esp32-wifi"
#define DT_N_S_wifi_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_wifi_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_wifi_P_compatible {"espressif,esp32-wifi"}
#define DT_N_S_wifi_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_wifi_P_compatible_IDX_0 "espressif,esp32-wifi"
#define DT_N_S_wifi_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-wifi
#define DT_N_S_wifi_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_wifi
#define DT_N_S_wifi_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_WIFI
#define DT_N_S_wifi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_wifi, compatible, 0)
#define DT_N_S_wifi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_wifi, compatible, 0)
#define DT_N_S_wifi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_wifi, compatible, 0, __VA_ARGS__)
#define DT_N_S_wifi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_wifi, compatible, 0, __VA_ARGS__)
#define DT_N_S_wifi_P_compatible_LEN 1
#define DT_N_S_wifi_P_compatible_EXISTS 1
#define DT_N_S_wifi_P_status "okay"
#define DT_N_S_wifi_P_status_STRING_UNQUOTED okay
#define DT_N_S_wifi_P_status_STRING_TOKEN okay
#define DT_N_S_wifi_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_wifi_P_status_IDX_0 "okay"
#define DT_N_S_wifi_P_status_IDX_0_EXISTS 1
#define DT_N_S_wifi_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_wifi_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_wifi_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_wifi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_wifi, status, 0)
#define DT_N_S_wifi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_wifi, status, 0)
#define DT_N_S_wifi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_wifi, status, 0, __VA_ARGS__)
#define DT_N_S_wifi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_wifi, status, 0, __VA_ARGS__)
#define DT_N_S_wifi_P_status_LEN 1
#define DT_N_S_wifi_P_status_EXISTS 1

/*
 * Devicetree node: /cpus
 *
 * Node identifier: DT_N_S_cpus
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_PATH "/cpus"

/* Node's name with unit-address: */
#define DT_N_S_cpus_FULL_NAME "cpus"
#define DT_N_S_cpus_FULL_NAME_UNQUOTED cpus
#define DT_N_S_cpus_FULL_NAME_TOKEN cpus
#define DT_N_S_cpus_FULL_NAME_UPPER_TOKEN CPUS

/* Node parent (/) identifier: */
#define DT_N_S_cpus_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_NODELABEL_NUM 0
#define DT_N_S_cpus_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_CHILD_NUM 3
#define DT_N_S_cpus_CHILD_NUM_STATUS_OKAY 3
#define DT_N_S_cpus_CHILD_UNIT_ADDR_INT_0 DT_N_S_cpus_S_cpu_0
#define DT_N_S_cpus_CHILD_UNIT_ADDR_INT_1 DT_N_S_cpus_S_cpu_1
#define DT_N_S_cpus_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_1) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_1) fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_HASH iL3XRGZVvvtpNJqKV0_jvtuXF7m6kgky4nI2ifizwdg

/* Node's dependency ordinal: */
#define DT_N_S_cpus_ORD 6
#define DT_N_S_cpus_ORD_STR_SORTABLE 00006

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_SUPPORTS_ORDS \
	7, /* /cpus/power-states */ \
	10, /* /cpus/cpu@0 */ \
	11, /* /cpus/cpu@1 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_REG_NUM 0
#define DT_N_S_cpus_FOREACH_REG(fn) 
#define DT_N_S_cpus_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_RANGES_NUM 0
#define DT_N_S_cpus_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_IRQ_NUM 0
#define DT_N_S_cpus_IRQ_LEVEL 0
#define DT_N_S_cpus_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states
 *
 * Node identifier: DT_N_S_cpus_S_power_states
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_PATH "/cpus/power-states"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_FULL_NAME "power-states"
#define DT_N_S_cpus_S_power_states_FULL_NAME_UNQUOTED power-states
#define DT_N_S_cpus_S_power_states_FULL_NAME_TOKEN power_states
#define DT_N_S_cpus_S_power_states_FULL_NAME_UPPER_TOKEN POWER_STATES

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_power_states_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_NODELABEL_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_CHILD_NUM 2
#define DT_N_S_cpus_S_power_states_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD(fn) fn(DT_N_S_cpus_S_power_states_S_light_sleep) fn(DT_N_S_cpus_S_power_states_S_deep_sleep)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_light_sleep) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_deep_sleep)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus_S_power_states_S_deep_sleep, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_cpus_S_power_states_S_light_sleep)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_light_sleep)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_HASH qMexuiO6C_SHOSQQCC_3by3odasm1z5VRx723zYLVgY

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_ORD 7
#define DT_N_S_cpus_S_power_states_ORD_STR_SORTABLE 00007

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_REQUIRES_ORDS \
	6, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_SUPPORTS_ORDS \
	8, /* /cpus/power-states/deep_sleep */ \
	9, /* /cpus/power-states/light_sleep */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_REG_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /cpus/power-states/deep_sleep
 *
 * Node identifier: DT_N_S_cpus_S_power_states_S_deep_sleep
 *
 * Binding (compatible = zephyr,power-state):
 *   $ZEPHYR_BASE/dts/bindings/power/zephyr,power-state.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_PATH "/cpus/power-states/deep_sleep"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FULL_NAME "deep_sleep"
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FULL_NAME_UNQUOTED deep_sleep
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FULL_NAME_TOKEN deep_sleep
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FULL_NAME_UPPER_TOKEN DEEP_SLEEP

/* Node parent (/cpus/power-states) identifier: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_PARENT DT_N_S_cpus_S_power_states

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_NODELABEL_NUM 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_NODELABEL(fn) fn(deep_sleep)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(deep_sleep, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_CHILD_NUM 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_HASH C7SKg2fWhdBJ3bgnNKxXYtXGHxBOLRajGXBHhDGlgA0

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_ORD 8
#define DT_N_S_cpus_S_power_states_S_deep_sleep_ORD_STR_SORTABLE 00008

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_REQUIRES_ORDS \
	7, /* /cpus/power-states */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_SUPPORTS_ORDS \
	10, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_EXISTS 1
#define DT_N_INST_1_zephyr_power_state DT_N_S_cpus_S_power_states_S_deep_sleep
#define DT_N_NODELABEL_deep_sleep      DT_N_S_cpus_S_power_states_S_deep_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_REG_NUM 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_S_deep_sleep_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_COMPAT_MATCHES_zephyr_power_state 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_cpus_S_power_states_S_deep_sleep_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_COMPAT_MODEL_IDX_0 "power-state"
#define DT_N_S_cpus_S_power_states_S_deep_sleep_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name "soft-off"
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_STRING_UNQUOTED soft-off
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_STRING_TOKEN soft_off
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_STRING_UPPER_TOKEN SOFT_OFF
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_IDX_0 "soft-off"
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_IDX_0_ENUM_IDX 6
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_IDX_0_ENUM_VAL_soft_off_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_ENUM_VAL_soft_off_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_LEN 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_power_state_name_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_zephyr_pm_device_disabled 0
#define DT_N_S_cpus_S_power_states_S_deep_sleep_P_zephyr_pm_device_disabled_EXISTS 1

/*
 * Devicetree node: /cpus/power-states/light_sleep
 *
 * Node identifier: DT_N_S_cpus_S_power_states_S_light_sleep
 *
 * Binding (compatible = zephyr,power-state):
 *   $ZEPHYR_BASE/dts/bindings/power/zephyr,power-state.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_PATH "/cpus/power-states/light_sleep"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_FULL_NAME "light_sleep"
#define DT_N_S_cpus_S_power_states_S_light_sleep_FULL_NAME_UNQUOTED light_sleep
#define DT_N_S_cpus_S_power_states_S_light_sleep_FULL_NAME_TOKEN light_sleep
#define DT_N_S_cpus_S_power_states_S_light_sleep_FULL_NAME_UPPER_TOKEN LIGHT_SLEEP

/* Node parent (/cpus/power-states) identifier: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_PARENT DT_N_S_cpus_S_power_states

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_NODELABEL_NUM 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_NODELABEL(fn) fn(light_sleep)
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_NODELABEL_VARGS(fn, ...) fn(light_sleep, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_power_states_S_light_sleep_CHILD_NUM 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_HASH trFhKUS39giGuBIU4RugUjCmoAFGXREORn8cmi85czc

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_ORD 9
#define DT_N_S_cpus_S_power_states_S_light_sleep_ORD_STR_SORTABLE 00009

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_REQUIRES_ORDS \
	7, /* /cpus/power-states */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_SUPPORTS_ORDS \
	10, /* /cpus/cpu@0 */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_EXISTS 1
#define DT_N_INST_0_zephyr_power_state DT_N_S_cpus_S_power_states_S_light_sleep
#define DT_N_NODELABEL_light_sleep     DT_N_S_cpus_S_power_states_S_light_sleep

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_REG_NUM 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_REG(fn) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_RANGES_NUM 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_power_states_S_light_sleep_IRQ_NUM 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_IRQ_LEVEL 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_COMPAT_MATCHES_zephyr_power_state 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_cpus_S_power_states_S_light_sleep_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_COMPAT_MODEL_IDX_0 "power-state"
#define DT_N_S_cpus_S_power_states_S_light_sleep_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name "standby"
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_STRING_UNQUOTED standby
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_STRING_TOKEN standby
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_STRING_UPPER_TOKEN STANDBY
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_IDX_0 "standby"
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_IDX_0_ENUM_IDX 3
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_IDX_0_ENUM_VAL_standby_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_ENUM_VAL_standby_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_power_states_S_light_sleep, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_power_states_S_light_sleep, power_state_name, 0)
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, power_state_name, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_LEN 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_power_state_name_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_min_residency_us 1000
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_min_residency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_exit_latency_us 50
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_exit_latency_us_EXISTS 1
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_zephyr_pm_device_disabled 0
#define DT_N_S_cpus_S_power_states_S_light_sleep_P_zephyr_pm_device_disabled_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@0
 *
 * Node identifier: DT_N_S_cpus_S_cpu_0
 *
 * Binding (compatible = espressif,xtensa-lx7):
 *   $ZEPHYR_BASE/dts/bindings/cpu/espressif,xtensa-lx7.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_0_PATH "/cpus/cpu@0"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0"
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UNQUOTED cpu@0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_TOKEN cpu_0
#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UPPER_TOKEN CPU_0

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_0_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL(fn) fn(cpu0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_cpu_0_HASH Su0JBbOtM0QIxe_1ka2Xvgw4rk1QaIlMIj8Rp_v4yVQ

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_0_ORD 10
#define DT_N_S_cpus_S_cpu_0_ORD_STR_SORTABLE 00010

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \
	6, /* /cpus */ \
	8, /* /cpus/power-states/deep_sleep */ \
	9, /* /cpus/power-states/light_sleep */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_0_EXISTS 1
#define DT_N_INST_0_espressif_xtensa_lx7 DT_N_S_cpus_S_cpu_0
#define DT_N_NODELABEL_cpu0              DT_N_S_cpus_S_cpu_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_0_REG_NUM 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG(fn) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, 0)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_0_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_espressif_xtensa_lx7 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_COMPAT_MODEL_IDX_0 "xtensa-lx7"
#define DT_N_S_cpus_S_cpu_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_0_P_clock_source 1
#define DT_N_S_cpus_S_cpu_0_P_clock_source_IDX_0_ENUM_IDX 1
#define DT_N_S_cpus_S_cpu_0_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_clock_source_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_clock_source_ENUM_VAL_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_clock_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq 40000000
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq_IDX_0_ENUM_IDX 0
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq_IDX_0_ENUM_VAL_40000000_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq_ENUM_VAL_40000000_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_xtal_freq_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_clock_frequency 240000000
#define DT_N_S_cpus_S_cpu_0_P_clock_frequency_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0 DT_N_S_cpus_S_power_states_S_light_sleep
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_PH DT_N_S_cpus_S_power_states_S_light_sleep
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1 DT_N_S_cpus_S_power_states_S_deep_sleep
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1_PH DT_N_S_cpus_S_power_states_S_deep_sleep
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_IDX_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0) \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__) \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_cpus_S_cpu_0, cpu_power_states, 1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_LEN 2
#define DT_N_S_cpus_S_cpu_0_P_cpu_power_states_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible {"espressif,xtensa-lx7"}
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "espressif,xtensa-lx7"
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED espressif,xtensa-lx7
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN espressif_xtensa_lx7
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_XTENSA_LX7
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */}
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /cpus/cpu@1
 *
 * Node identifier: DT_N_S_cpus_S_cpu_1
 *
 * Binding (compatible = espressif,xtensa-lx7):
 *   $ZEPHYR_BASE/dts/bindings/cpu/espressif,xtensa-lx7.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_cpus_S_cpu_1_PATH "/cpus/cpu@1"

/* Node's name with unit-address: */
#define DT_N_S_cpus_S_cpu_1_FULL_NAME "cpu@1"
#define DT_N_S_cpus_S_cpu_1_FULL_NAME_UNQUOTED cpu@1
#define DT_N_S_cpus_S_cpu_1_FULL_NAME_TOKEN cpu_1
#define DT_N_S_cpus_S_cpu_1_FULL_NAME_UPPER_TOKEN CPU_1

/* Node parent (/cpus) identifier: */
#define DT_N_S_cpus_S_cpu_1_PARENT DT_N_S_cpus

/* Node's index in its parent's list of children: */
#define DT_N_S_cpus_S_cpu_1_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_cpus_S_cpu_1_NODELABEL_NUM 1
#define DT_N_S_cpus_S_cpu_1_FOREACH_NODELABEL(fn) fn(cpu1)
#define DT_N_S_cpus_S_cpu_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(cpu1, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_cpus) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_cpus_S_cpu_1_CHILD_NUM 0
#define DT_N_S_cpus_S_cpu_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD(fn) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_cpus_S_cpu_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_cpus_S_cpu_1_HASH 9JjWVNk3G1ibyc8ZwlqKxfoxH3N71yBfTFpYJTDe_oU

/* Node's dependency ordinal: */
#define DT_N_S_cpus_S_cpu_1_ORD 11
#define DT_N_S_cpus_S_cpu_1_ORD_STR_SORTABLE 00011

/* Ordinals for what this node depends on directly: */
#define DT_N_S_cpus_S_cpu_1_REQUIRES_ORDS \
	6, /* /cpus */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_cpus_S_cpu_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_cpus_S_cpu_1_EXISTS 1
#define DT_N_INST_1_espressif_xtensa_lx7 DT_N_S_cpus_S_cpu_1
#define DT_N_NODELABEL_cpu1              DT_N_S_cpus_S_cpu_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_cpus_S_cpu_1_REG_NUM 1
#define DT_N_S_cpus_S_cpu_1_REG_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */
#define DT_N_S_cpus_S_cpu_1_FOREACH_REG(fn) fn(DT_N_S_cpus_S_cpu_1, 0)
#define DT_N_S_cpus_S_cpu_1_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_1, 0)
#define DT_N_S_cpus_S_cpu_1_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_1, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_1_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_1, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_1_RANGES_NUM 0
#define DT_N_S_cpus_S_cpu_1_FOREACH_RANGE(fn) 
#define DT_N_S_cpus_S_cpu_1_IRQ_NUM 0
#define DT_N_S_cpus_S_cpu_1_IRQ_LEVEL 0
#define DT_N_S_cpus_S_cpu_1_COMPAT_MATCHES_espressif_xtensa_lx7 1
#define DT_N_S_cpus_S_cpu_1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_cpus_S_cpu_1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_COMPAT_MODEL_IDX_0 "xtensa-lx7"
#define DT_N_S_cpus_S_cpu_1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_cpus_S_cpu_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_cpus_S_cpu_1_P_clock_source 1
#define DT_N_S_cpus_S_cpu_1_P_clock_source_IDX_0_ENUM_IDX 1
#define DT_N_S_cpus_S_cpu_1_P_clock_source_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_clock_source_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_clock_source_ENUM_VAL_1_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_clock_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq 40000000
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq_IDX_0_ENUM_IDX 0
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq_IDX_0_ENUM_VAL_40000000_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq_ENUM_VAL_40000000_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_xtal_freq_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_clock_frequency 240000000
#define DT_N_S_cpus_S_cpu_1_P_clock_frequency_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_compatible {"espressif,xtensa-lx7"}
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0 "espressif,xtensa-lx7"
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0_STRING_UNQUOTED espressif,xtensa-lx7
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0_STRING_TOKEN espressif_xtensa_lx7
#define DT_N_S_cpus_S_cpu_1_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_XTENSA_LX7
#define DT_N_S_cpus_S_cpu_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_1, compatible, 0)
#define DT_N_S_cpus_S_cpu_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_1, compatible, 0)
#define DT_N_S_cpus_S_cpu_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_cpus_S_cpu_1_P_compatible_LEN 1
#define DT_N_S_cpus_S_cpu_1_P_compatible_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_reg {1 /* 0x1 */}
#define DT_N_S_cpus_S_cpu_1_P_reg_IDX_0_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_reg_IDX_0 1
#define DT_N_S_cpus_S_cpu_1_P_reg_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_zephyr_deferred_init 0
#define DT_N_S_cpus_S_cpu_1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_wakeup_source 0
#define DT_N_S_cpus_S_cpu_1_P_wakeup_source_EXISTS 1
#define DT_N_S_cpus_S_cpu_1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_cpus_S_cpu_1_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc
 *
 * Node identifier: DT_N_S_soc
 */

/* Node's full path: */
#define DT_N_S_soc_PATH "/soc"

/* Node's name with unit-address: */
#define DT_N_S_soc_FULL_NAME "soc"
#define DT_N_S_soc_FULL_NAME_UNQUOTED soc
#define DT_N_S_soc_FULL_NAME_TOKEN soc
#define DT_N_S_soc_FULL_NAME_UPPER_TOKEN SOC

/* Node parent (/) identifier: */
#define DT_N_S_soc_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_NODELABEL_NUM 0
#define DT_N_S_soc_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_CHILD_NUM 48
#define DT_N_S_soc_CHILD_NUM_STATUS_OKAY 25
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1107296256 DT_N_S_soc_S_memory_42000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1006632960 DT_N_S_soc_S_memory_3c000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1077346304 DT_N_S_soc_S_memory_40370000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070104576 DT_N_S_soc_S_memory_3fc88000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070530560 DT_N_S_soc_S_memory_3fcf0000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070485504 DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070486528 DT_N_S_soc_S_memory_3fce5400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070502912 DT_N_S_soc_S_ipm_3fce9400
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1070502920 DT_N_S_soc_S_mbox_3fce9408
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1342177280 DT_N_S_soc_S_memory_50000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1611653120 DT_N_S_soc_S_memory_600fe000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1611407360 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610747908 DT_N_S_soc_S_xt_wdt_60021004
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610645508 DT_N_S_soc_S_rtc_timer_60008004
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610620928 DT_N_S_soc_S_flash_controller_60002000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610612736 DT_N_S_soc_S_uart_60000000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610678272 DT_N_S_soc_S_uart_60010000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610801152 DT_N_S_soc_S_uart_6002e000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610647644 DT_N_S_soc_S_touch_6000885c
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610690560 DT_N_S_soc_S_i2c_60013000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610772480 DT_N_S_soc_S_i2c_60027000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610674176 DT_N_S_soc_S_i2s_6000f000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610797056 DT_N_S_soc_S_i2s_6002d000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610760192 DT_N_S_soc_S_spi_60024000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610764288 DT_N_S_soc_S_spi_60025000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610647552 DT_N_S_soc_S_coretemp_60008800
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610874880 DT_N_S_soc_S_adc_60040000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610874884 DT_N_S_soc_S_adc_60040004
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610788864 DT_N_S_soc_S_can_6002b000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610878976 DT_N_S_soc_S_lcd_cam_60041000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610842112 DT_N_S_soc_S_uart_60038000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1611137024 DT_N_S_soc_S_usb_otg_60080000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610739712 DT_N_S_soc_S_counter_6001f000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610739748 DT_N_S_soc_S_counter_6001f024
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610743808 DT_N_S_soc_S_counter_60020000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610743844 DT_N_S_soc_S_counter_60020024
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610739784 DT_N_S_soc_S_watchdog_6001f048
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610743880 DT_N_S_soc_S_watchdog_60020048
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610829948 DT_N_S_soc_S_trng_6003507c
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610715136 DT_N_S_soc_S_ledc_60019000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610735616 DT_N_S_soc_S_mcpwm_6001e000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610792960 DT_N_S_soc_S_mcpwm_6002c000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610706944 DT_N_S_soc_S_pcnt_60017000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610870784 DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610776576 DT_N_S_soc_S_sdhc_60028000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610854400 DT_N_S_soc_S_sha_6003b000
#define DT_N_S_soc_CHILD_UNIT_ADDR_INT_1610850304 DT_N_S_soc_S_aes_6003a000
#define DT_N_S_soc_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_memory_42000000) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_3fce5000) fn(DT_N_S_soc_S_memory_3fce5400) fn(DT_N_S_soc_S_ipm_3fce9400) fn(DT_N_S_soc_S_mbox_3fce9408) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000) fn(DT_N_S_soc_S_interrupt_controller_600c2000) fn(DT_N_S_soc_S_xt_wdt_60021004) fn(DT_N_S_soc_S_rtc_timer_60008004) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc_S_uart_60000000) fn(DT_N_S_soc_S_uart_60010000) fn(DT_N_S_soc_S_uart_6002e000) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc_S_touch_6000885c) fn(DT_N_S_soc_S_i2c_60013000) fn(DT_N_S_soc_S_i2c_60027000) fn(DT_N_S_soc_S_i2s_6000f000) fn(DT_N_S_soc_S_i2s_6002d000) fn(DT_N_S_soc_S_spi_60024000) fn(DT_N_S_soc_S_spi_60025000) fn(DT_N_S_soc_S_coretemp_60008800) fn(DT_N_S_soc_S_adc_60040000) fn(DT_N_S_soc_S_adc_60040004) fn(DT_N_S_soc_S_can_6002b000) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc_S_uart_60038000) fn(DT_N_S_soc_S_usb_otg_60080000) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc_S_counter_60020000) fn(DT_N_S_soc_S_counter_60020024) fn(DT_N_S_soc_S_watchdog_6001f048) fn(DT_N_S_soc_S_watchdog_60020048) fn(DT_N_S_soc_S_trng_6003507c) fn(DT_N_S_soc_S_ledc_60019000) fn(DT_N_S_soc_S_mcpwm_6001e000) fn(DT_N_S_soc_S_mcpwm_6002c000) fn(DT_N_S_soc_S_pcnt_60017000) fn(DT_N_S_soc_S_dma_6003f000) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc_S_sha_6003b000) fn(DT_N_S_soc_S_aes_6003a000)
#define DT_N_S_soc_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_memory_42000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3c000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40370000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fc88000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fcf0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ipm_3fce9400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mbox_3fce9408) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_600fe000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_600c2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_xt_wdt_60021004) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_timer_60008004) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60010000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_6002e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_touch_6000885c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60027000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_6000f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_6002d000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60024000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60025000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_coretemp_60008800) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_60040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_60040004) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_6002b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60038000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_otg_60080000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f024) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020024) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_6001f048) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_60020048) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_trng_6003507c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ledc_60019000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mcpwm_6001e000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mcpwm_6002c000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pcnt_60017000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_6003f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sha_6003b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_aes_6003a000)
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) fn(DT_N_S_soc_S_ipm_3fce9400, __VA_ARGS__) fn(DT_N_S_soc_S_mbox_3fce9408, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) fn(DT_N_S_soc_S_xt_wdt_60021004, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_timer_60008004, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60010000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_6002e000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio, __VA_ARGS__) fn(DT_N_S_soc_S_touch_6000885c, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60027000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_6000f000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_6002d000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60025000, __VA_ARGS__) fn(DT_N_S_soc_S_coretemp_60008800, __VA_ARGS__) fn(DT_N_S_soc_S_adc_60040000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_60040004, __VA_ARGS__) fn(DT_N_S_soc_S_can_6002b000, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_otg_60080000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_60020048, __VA_ARGS__) fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) fn(DT_N_S_soc_S_ledc_60019000, __VA_ARGS__) fn(DT_N_S_soc_S_mcpwm_6001e000, __VA_ARGS__) fn(DT_N_S_soc_S_mcpwm_6002c000, __VA_ARGS__) fn(DT_N_S_soc_S_pcnt_60017000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_6003f000, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ipm_3fce9400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mbox_3fce9408, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_xt_wdt_60021004, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_rtc_timer_60008004, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60010000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_6002e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_touch_6000885c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60027000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_6000f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2s_6002d000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60025000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_coretemp_60008800, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_60040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_adc_60040004, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_can_6002b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_usb_otg_60080000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_60020048, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_ledc_60019000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mcpwm_6001e000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_mcpwm_6002c000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_pcnt_60017000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_dma_6003f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_memory_42000000) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_3fce5000) fn(DT_N_S_soc_S_memory_3fce5400) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000) fn(DT_N_S_soc_S_interrupt_controller_600c2000) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc_S_uart_60000000) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc_S_i2c_60013000) fn(DT_N_S_soc_S_spi_60024000) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc_S_uart_60038000) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc_S_counter_60020024) fn(DT_N_S_soc_S_watchdog_6001f048) fn(DT_N_S_soc_S_trng_6003507c) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc_S_sha_6003b000) fn(DT_N_S_soc_S_aes_6003a000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_memory_42000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3c000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40370000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fc88000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fcf0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5400) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_50000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_600fe000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_600c2000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60013000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60024000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60038000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f024) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020024) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_6001f048) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_trng_6003507c) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sha_6003b000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_aes_6003a000)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__)
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_HASH DcVqqq9YzG86l3_Hk7pNncUh2rnHG8USjbVY6wBdFts

/* Node's dependency ordinal: */
#define DT_N_S_soc_ORD 12
#define DT_N_S_soc_ORD_STR_SORTABLE 00012

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_SUPPORTS_ORDS \
	13, /* /soc/gpio */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	35, /* /soc/adc@60040000 */ \
	36, /* /soc/adc@60040004 */ \
	37, /* /soc/aes@6003a000 */ \
	38, /* /soc/can@6002b000 */ \
	39, /* /soc/coretemp@60008800 */ \
	40, /* /soc/i2c@60013000 */ \
	41, /* /soc/i2c@60027000 */ \
	42, /* /soc/dma@6003f000 */ \
	43, /* /soc/i2s@6000f000 */ \
	44, /* /soc/i2s@6002d000 */ \
	45, /* /soc/memory@3fce5000 */ \
	46, /* /soc/ipm@3fce9400 */ \
	47, /* /soc/ledc@60019000 */ \
	48, /* /soc/mbox@3fce9408 */ \
	49, /* /soc/mcpwm@6001e000 */ \
	50, /* /soc/mcpwm@6002c000 */ \
	51, /* /soc/memory@3fc88000 */ \
	52, /* /soc/memory@3fce5400 */ \
	53, /* /soc/memory@3fcf0000 */ \
	54, /* /soc/memory@40370000 */ \
	55, /* /soc/memory@42000000 */ \
	56, /* /soc/memory@50000000 */ \
	57, /* /soc/memory@600fe000 */ \
	58, /* /soc/pcnt@60017000 */ \
	59, /* /soc/rtc_timer@60008004 */ \
	60, /* /soc/sha@6003b000 */ \
	61, /* /soc/spi@60025000 */ \
	62, /* /soc/touch@6000885c */ \
	63, /* /soc/trng@6003507c */ \
	64, /* /soc/uart@60000000 */ \
	65, /* /soc/uart@60010000 */ \
	66, /* /soc/uart@6002e000 */ \
	67, /* /soc/uart@60038000 */ \
	68, /* /soc/usb_otg@60080000 */ \
	69, /* /soc/watchdog@6001f048 */ \
	70, /* /soc/watchdog@60020048 */ \
	71, /* /soc/xt_wdt@60021004 */ \
	72, /* /soc/counter@6001f000 */ \
	74, /* /soc/counter@6001f024 */ \
	76, /* /soc/counter@60020000 */ \
	78, /* /soc/counter@60020024 */ \
	80, /* /soc/flash-controller@60002000 */ \
	95, /* /soc/lcd_cam@60041000 */ \
	98, /* /soc/memory@3c000000 */ \
	100, /* /soc/sdhc@60028000 */ \
	103, /* /soc/spi@60024000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_EXISTS 1
#define DT_N_INST_0_simple_bus DT_N_S_soc

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_REG_NUM 0
#define DT_N_S_soc_FOREACH_REG(fn) 
#define DT_N_S_soc_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_RANGES_NUM 0
#define DT_N_S_soc_FOREACH_RANGE(fn) 
#define DT_N_S_soc_IRQ_NUM 0
#define DT_N_S_soc_IRQ_LEVEL 0
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_P_compatible {"simple-bus"}
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_P_compatible_IDX_0 "simple-bus"
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN simple_bus
#define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc, compatible, 0)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_P_compatible_LEN 1
#define DT_N_S_soc_P_compatible_EXISTS 1
#define DT_N_S_soc_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/gpio
 *
 * Node identifier: DT_N_S_soc_S_gpio
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpio_PATH "/soc/gpio"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpio_FULL_NAME "gpio"
#define DT_N_S_soc_S_gpio_FULL_NAME_UNQUOTED gpio
#define DT_N_S_soc_S_gpio_FULL_NAME_TOKEN gpio
#define DT_N_S_soc_S_gpio_FULL_NAME_UPPER_TOKEN GPIO

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_gpio_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpio_CHILD_IDX 18

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_gpio_NODELABEL_NUM 1
#define DT_N_S_soc_S_gpio_FOREACH_NODELABEL(fn) fn(gpio)
#define DT_N_S_soc_S_gpio_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpio_CHILD_NUM 2
#define DT_N_S_soc_S_gpio_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_soc_S_gpio_CHILD_UNIT_ADDR_INT_1610629120 DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_gpio_CHILD_UNIT_ADDR_INT_1610631168 DT_N_S_soc_S_gpio_S_gpio_60004800
#define DT_N_S_soc_S_gpio_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) fn(DT_N_S_soc_S_gpio_S_gpio_60004800)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_S_gpio_60004800)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) fn(DT_N_S_soc_S_gpio_S_gpio_60004800)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_S_gpio_60004800)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_gpio_HASH _Rog3Qc6JJHktlTnUGxRyVgQ8fH7dhqdBaaNvGKrX_E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_ORD 13
#define DT_N_S_soc_S_gpio_ORD_STR_SORTABLE 00013

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_SUPPORTS_ORDS \
	15, /* /soc/gpio/gpio@60004000 */ \
	94, /* /soc/gpio/gpio@60004800 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_EXISTS 1
#define DT_N_INST_1_simple_bus DT_N_S_soc_S_gpio
#define DT_N_NODELABEL_gpio    DT_N_S_soc_S_gpio

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpio_REG_NUM 0
#define DT_N_S_soc_S_gpio_FOREACH_REG(fn) 
#define DT_N_S_soc_S_gpio_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpio_RANGES_NUM 0
#define DT_N_S_soc_S_gpio_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpio_IRQ_NUM 0
#define DT_N_S_soc_S_gpio_IRQ_LEVEL 0
#define DT_N_S_soc_S_gpio_COMPAT_MATCHES_simple_bus 1
#define DT_N_S_soc_S_gpio_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpio_PINCTRL_NUM 0

/* Map properties: */
#define DT_N_S_soc_S_gpio_P_gpio_map_LEN 2
#define DT_N_S_soc_S_gpio_P_gpio_map_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_ADDRESS_LEN 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_LEN 2
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_0 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_ADDRESS_LEN 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_LEN 2
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_0_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_ADDRESS_LEN 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_LEN 2
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_0 32
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_CHILD_SPECIFIER_IDX_1 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT DT_N_S_soc_S_gpio_S_gpio_60004800
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_ADDRESS_LEN 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_LEN 2
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_0 0
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_P_gpio_map_MAP_ENTRY_1_PARENT_SPECIFIER_IDX_1 0
#define DT_N_S_soc_S_gpio_P_gpio_map_FOREACH_MAP_ENTRY(fn) fn(DT_N_S_soc_S_gpio, gpio_map, 0) \
	fn(DT_N_S_soc_S_gpio, gpio_map, 1)
#define DT_N_S_soc_S_gpio_P_gpio_map_FOREACH_MAP_ENTRY_SEP(fn, sep) fn(DT_N_S_soc_S_gpio, gpio_map, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio, gpio_map, 1)
#define DT_N_S_soc_S_gpio_P_gpio_map_FOREACH_MAP_ENTRY_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio, gpio_map, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_gpio, gpio_map, 1, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_P_gpio_map_FOREACH_MAP_ENTRY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio, gpio_map, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_gpio, gpio_map, 1, __VA_ARGS__)

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_P_compatible {"simple-bus"}
#define DT_N_S_soc_S_gpio_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_P_compatible_IDX_0 "simple-bus"
#define DT_N_S_soc_S_gpio_P_compatible_IDX_0_STRING_UNQUOTED simple-bus
#define DT_N_S_soc_S_gpio_P_compatible_IDX_0_STRING_TOKEN simple_bus
#define DT_N_S_soc_S_gpio_P_compatible_IDX_0_STRING_UPPER_TOKEN SIMPLE_BUS
#define DT_N_S_soc_S_gpio_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio, compatible, 0)
#define DT_N_S_soc_S_gpio_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio, compatible, 0)
#define DT_N_S_soc_S_gpio_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpio_P_ranges_EXISTS 1

/*
 * Devicetree node: /soc/interrupt-controller@600c2000
 *
 * Node identifier: DT_N_S_soc_S_interrupt_controller_600c2000
 *
 * Binding (compatible = espressif,esp32-intc):
 *   $ZEPHYR_BASE/dts/bindings/interrupt-controller/espressif,esp32-intc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_PATH "/soc/interrupt-controller@600c2000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_FULL_NAME "interrupt-controller@600c2000"
#define DT_N_S_soc_S_interrupt_controller_600c2000_FULL_NAME_UNQUOTED interrupt-controller@600c2000
#define DT_N_S_soc_S_interrupt_controller_600c2000_FULL_NAME_TOKEN interrupt_controller_600c2000
#define DT_N_S_soc_S_interrupt_controller_600c2000_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_600C2000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_CHILD_IDX 11

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_NODELABEL_NUM 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_NODELABEL(fn) fn(intc)
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_NODELABEL_VARGS(fn, ...) fn(intc, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_interrupt_controller_600c2000_CHILD_NUM 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_HASH aa_5tLsFNt_1Ms9EfqWWh5Pcx4U3A5ZqRyYhanacFig

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_ORD 14
#define DT_N_S_soc_S_interrupt_controller_600c2000_ORD_STR_SORTABLE 00014

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_SUPPORTS_ORDS \
	15, /* /soc/gpio/gpio@60004000 */ \
	38, /* /soc/can@6002b000 */ \
	40, /* /soc/i2c@60013000 */ \
	41, /* /soc/i2c@60027000 */ \
	42, /* /soc/dma@6003f000 */ \
	43, /* /soc/i2s@6000f000 */ \
	44, /* /soc/i2s@6002d000 */ \
	46, /* /soc/ipm@3fce9400 */ \
	48, /* /soc/mbox@3fce9408 */ \
	49, /* /soc/mcpwm@6001e000 */ \
	50, /* /soc/mcpwm@6002c000 */ \
	58, /* /soc/pcnt@60017000 */ \
	59, /* /soc/rtc_timer@60008004 */ \
	61, /* /soc/spi@60025000 */ \
	62, /* /soc/touch@6000885c */ \
	64, /* /soc/uart@60000000 */ \
	65, /* /soc/uart@60010000 */ \
	66, /* /soc/uart@6002e000 */ \
	67, /* /soc/uart@60038000 */ \
	68, /* /soc/usb_otg@60080000 */ \
	69, /* /soc/watchdog@6001f048 */ \
	70, /* /soc/watchdog@60020048 */ \
	71, /* /soc/xt_wdt@60021004 */ \
	72, /* /soc/counter@6001f000 */ \
	74, /* /soc/counter@6001f024 */ \
	76, /* /soc/counter@60020000 */ \
	78, /* /soc/counter@60020024 */ \
	94, /* /soc/gpio/gpio@60004800 */ \
	95, /* /soc/lcd_cam@60041000 */ \
	100, /* /soc/sdhc@60028000 */ \
	103, /* /soc/spi@60024000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_intc DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_NODELABEL_intc              DT_N_S_soc_S_interrupt_controller_600c2000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_REG_NUM 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_REG_IDX_0_VAL_ADDRESS 1611407360 /* 0x600c2000 */
#define DT_N_S_soc_S_interrupt_controller_600c2000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_REG(fn) fn(DT_N_S_soc_S_interrupt_controller_600c2000, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_600c2000, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_RANGES_NUM 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_interrupt_controller_600c2000_IRQ_NUM 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_IRQ_LEVEL 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_COMPAT_MATCHES_espressif_esp32_intc 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_interrupt_controller_600c2000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_COMPAT_MODEL_IDX_0 "esp32-intc"
#define DT_N_S_soc_S_interrupt_controller_600c2000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg {1611407360 /* 0x600c2000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg_IDX_0 1611407360
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_reg_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_interrupt_controller 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_interrupt_controller_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status "okay"
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_600c2000, status, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_600c2000, status, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_LEN 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_status_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible {"espressif,esp32-intc"}
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_IDX_0 "espressif,esp32-intc"
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-intc
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_intc
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_INTC
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_600c2000, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_600c2000, compatible, 0)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_LEN 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_wakeup_source 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_interrupt_controller_600c2000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/gpio/gpio@60004000
 *
 * Node identifier: DT_N_S_soc_S_gpio_S_gpio_60004000
 *
 * Binding (compatible = espressif,esp32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/espressif,esp32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_PATH "/soc/gpio/gpio@60004000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FULL_NAME "gpio@60004000"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FULL_NAME_UNQUOTED gpio@60004000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FULL_NAME_TOKEN gpio_60004000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FULL_NAME_UPPER_TOKEN GPIO_60004000

/* Node parent (/soc/gpio) identifier: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_PARENT DT_N_S_soc_S_gpio

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_NODELABEL_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_NODELABEL(fn) fn(gpio0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_CHILD_NUM 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_HASH xpyrJ0_bMgu640HOnNuFv0VJvKP3RQSicpWnLHTEkZ8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_ORD 15
#define DT_N_S_soc_S_gpio_S_gpio_60004000_ORD_STR_SORTABLE 00015

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_REQUIRES_ORDS \
	13, /* /soc/gpio */ \
	14, /* /soc/interrupt-controller@600c2000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_SUPPORTS_ORDS \
	16, /* /leds */ \
	17, /* /leds/led_0 */ \
	103, /* /soc/spi@60024000 */ \
	104, /* /soc/spi@60024000/lora@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_gpio DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_NODELABEL_gpio0             DT_N_S_soc_S_gpio_S_gpio_60004000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_REG_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_REG_IDX_0_VAL_ADDRESS 1610629120 /* 0x60004000 */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_REG_IDX_0_VAL_SIZE 2048 /* 0x800 */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_REG(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_RANGES_NUM 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_IRQ_LEVEL 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_COMPAT_MATCHES_espressif_esp32_gpio 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_COMPAT_MODEL_IDX_0 "esp32-gpio"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg {1610629120 /* 0x60004000 */, 2048 /* 0x800 */}
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg_IDX_0 1610629120
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg_IDX_1 2048
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_ngpios 32
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status "okay"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, status, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, status, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible {"espressif,esp32-gpio"}
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_IDX_0 "espressif,esp32-gpio"
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-gpio
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_gpio
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_GPIO
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, compatible, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, compatible, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts {16 /* 0x10 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, interrupt_parent, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, interrupt_parent, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_wakeup_source 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpio_S_gpio_60004000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /leds
 *
 * Node identifier: DT_N_S_leds
 *
 * Binding (compatible = gpio-leds):
 *   $ZEPHYR_BASE/dts/bindings/led/gpio-leds.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_PATH "/leds"

/* Node's name with unit-address: */
#define DT_N_S_leds_FULL_NAME "leds"
#define DT_N_S_leds_FULL_NAME_UNQUOTED leds
#define DT_N_S_leds_FULL_NAME_TOKEN leds
#define DT_N_S_leds_FULL_NAME_UPPER_TOKEN LEDS

/* Node parent (/) identifier: */
#define DT_N_S_leds_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_NODELABEL_NUM 0
#define DT_N_S_leds_FOREACH_NODELABEL(fn) 
#define DT_N_S_leds_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_leds_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_CHILD_NUM 1
#define DT_N_S_leds_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_leds_FOREACH_CHILD(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_leds_S_led_0)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_leds_HASH bMroFUocDdjE3kJ38dK18mDvlCOPoyya5kIIs76irj8

/* Node's dependency ordinal: */
#define DT_N_S_leds_ORD 16
#define DT_N_S_leds_ORD_STR_SORTABLE 00016

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_REQUIRES_ORDS \
	0, /* / */ \
	15, /* /soc/gpio/gpio@60004000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_SUPPORTS_ORDS \
	17, /* /leds/led_0 */

/* Existence and alternate IDs: */
#define DT_N_S_leds_EXISTS 1
#define DT_N_INST_0_gpio_leds DT_N_S_leds

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_REG_NUM 0
#define DT_N_S_leds_FOREACH_REG(fn) 
#define DT_N_S_leds_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_RANGES_NUM 0
#define DT_N_S_leds_FOREACH_RANGE(fn) 
#define DT_N_S_leds_IRQ_NUM 0
#define DT_N_S_leds_IRQ_LEVEL 0
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds 1
#define DT_N_S_leds_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_P_compatible {"gpio-leds"}
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds"
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds
#define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
#define DT_N_S_leds_P_compatible_LEN 1
#define DT_N_S_leds_P_compatible_EXISTS 1

/*
 * Devicetree node: /leds/led_0
 *
 * Node identifier: DT_N_S_leds_S_led_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_leds_S_led_0_PATH "/leds/led_0"

/* Node's name with unit-address: */
#define DT_N_S_leds_S_led_0_FULL_NAME "led_0"
#define DT_N_S_leds_S_led_0_FULL_NAME_UNQUOTED led_0
#define DT_N_S_leds_S_led_0_FULL_NAME_TOKEN led_0
#define DT_N_S_leds_S_led_0_FULL_NAME_UPPER_TOKEN LED_0

/* Node parent (/leds) identifier: */
#define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds

/* Node's index in its parent's list of children: */
#define DT_N_S_leds_S_led_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_leds_S_led_0_NODELABEL_NUM 1
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL(fn) fn(led0)
#define DT_N_S_leds_S_led_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(led0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_leds) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_leds_S_led_0_CHILD_NUM 0
#define DT_N_S_leds_S_led_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_leds_S_led_0_HASH kqSZv01Dnr_1hPdmxPVlr9u8kLMk_UWHIyVHG3GknSY

/* Node's dependency ordinal: */
#define DT_N_S_leds_S_led_0_ORD 17
#define DT_N_S_leds_S_led_0_ORD_STR_SORTABLE 00017

/* Ordinals for what this node depends on directly: */
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS \
	15, /* /soc/gpio/gpio@60004000 */ \
	16, /* /leds */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_leds_S_led_0_EXISTS 1
#define DT_N_ALIAS_led0     DT_N_S_leds_S_led_0
#define DT_N_NODELABEL_led0 DT_N_S_leds_S_led_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_leds_S_led_0_REG_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_REG(fn) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_leds_S_led_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_leds_S_led_0_RANGES_NUM 0
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn) 
#define DT_N_S_leds_S_led_0_IRQ_NUM 0
#define DT_N_S_leds_S_led_0_IRQ_LEVEL 0
#define DT_N_S_leds_S_led_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_leds_S_led_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin 21
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_leds_S_led_0, gpios, 0, pin) \
	fn(DT_N_S_leds_S_led_0, gpios, 0, flags)
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_leds_S_led_0, gpios, 0, flags)
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, gpios, 0)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_gpios_LEN 1
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label "BUILTIN LED"
#define DT_N_S_leds_S_led_0_P_label_STRING_UNQUOTED BUILTIN LED
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN BUILTIN_LED
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN BUILTIN_LED
#define DT_N_S_leds_S_led_0_P_label_IDX_0 "BUILTIN LED"
#define DT_N_S_leds_S_led_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds_S_led_0, label, 0)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__)
#define DT_N_S_leds_S_led_0_P_label_LEN 1
#define DT_N_S_leds_S_led_0_P_label_EXISTS 1

/*
 * Devicetree node: /pin-controller
 *
 * Node identifier: DT_N_S_pin_controller
 *
 * Binding (compatible = espressif,esp32-pinctrl):
 *   $ZEPHYR_BASE/dts/bindings/pinctrl/espressif,esp32-pinctrl.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_PATH "/pin-controller"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_FULL_NAME "pin-controller"
#define DT_N_S_pin_controller_FULL_NAME_UNQUOTED pin-controller
#define DT_N_S_pin_controller_FULL_NAME_TOKEN pin_controller
#define DT_N_S_pin_controller_FULL_NAME_UPPER_TOKEN PIN_CONTROLLER

/* Node parent (/) identifier: */
#define DT_N_S_pin_controller_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_NODELABEL_NUM 1
#define DT_N_S_pin_controller_FOREACH_NODELABEL(fn) fn(pinctrl)
#define DT_N_S_pin_controller_FOREACH_NODELABEL_VARGS(fn, ...) fn(pinctrl, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_CHILD_NUM 6
#define DT_N_S_pin_controller_CHILD_NUM_STATUS_OKAY 6
#define DT_N_S_pin_controller_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller_S_twai_default)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_twai_default)
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller_S_twai_default)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_twai_default)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__)
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_HASH bWf59uCG_pY5hQAcoRx7FSfuctl8KNxAtmdgsI6QClA

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_ORD 18
#define DT_N_S_pin_controller_ORD_STR_SORTABLE 00018

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_SUPPORTS_ORDS \
	19, /* /pin-controller/i2c0_default */ \
	21, /* /pin-controller/i2c1_default */ \
	23, /* /pin-controller/lcd_cam_default */ \
	26, /* /pin-controller/spim2_default */ \
	29, /* /pin-controller/twai_default */ \
	31, /* /pin-controller/uart0_default */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_EXISTS 1
#define DT_N_INST_0_espressif_esp32_pinctrl DT_N_S_pin_controller
#define DT_N_NODELABEL_pinctrl              DT_N_S_pin_controller

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_REG_NUM 0
#define DT_N_S_pin_controller_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_RANGES_NUM 0
#define DT_N_S_pin_controller_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_IRQ_NUM 0
#define DT_N_S_pin_controller_IRQ_LEVEL 0
#define DT_N_S_pin_controller_COMPAT_MATCHES_espressif_esp32_pinctrl 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_COMPAT_MODEL_IDX_0 "esp32-pinctrl"
#define DT_N_S_pin_controller_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_P_status "okay"
#define DT_N_S_pin_controller_P_status_STRING_UNQUOTED okay
#define DT_N_S_pin_controller_P_status_STRING_TOKEN okay
#define DT_N_S_pin_controller_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_pin_controller_P_status_IDX_0 "okay"
#define DT_N_S_pin_controller_P_status_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_pin_controller_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_pin_controller_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_pin_controller_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, status, 0)
#define DT_N_S_pin_controller_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, status, 0)
#define DT_N_S_pin_controller_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, status, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, status, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_status_LEN 1
#define DT_N_S_pin_controller_P_status_EXISTS 1
#define DT_N_S_pin_controller_P_compatible {"espressif,esp32-pinctrl"}
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_P_compatible_IDX_0 "espressif,esp32-pinctrl"
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_pinctrl
#define DT_N_S_pin_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_PINCTRL
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller, compatible, 0)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_P_compatible_LEN 1
#define DT_N_S_pin_controller_P_compatible_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_deferred_init 0
#define DT_N_S_pin_controller_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_pin_controller_P_wakeup_source 0
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS 1
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_pin_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_PATH "/pin-controller/i2c0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME "i2c0_default"
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME_UNQUOTED i2c0_default
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME_TOKEN i2c0_default
#define DT_N_S_pin_controller_S_i2c0_default_FULL_NAME_UPPER_TOKEN I2C0_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_NODELABEL(fn) fn(i2c0_default)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c0_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_i2c0_default_HASH jwLAya2l1n5eq23pU58aJBqJOApGFQeY8GlS09jN_X8

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_ORD 19
#define DT_N_S_pin_controller_S_i2c0_default_ORD_STR_SORTABLE 00019

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_SUPPORTS_ORDS \
	20, /* /pin-controller/i2c0_default/group1 */ \
	40, /* /soc/i2c@60013000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_EXISTS 1
#define DT_N_NODELABEL_i2c0_default DT_N_S_pin_controller_S_i2c0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PATH "/pin-controller/i2c0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/i2c0_default) identifier: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_HASH _HSqkKDjPxhuu0z84CDy13StRYiLrOnhQel0xHxUxuM

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD 20
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_ORD_STR_SORTABLE 00020

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REQUIRES_ORDS \
	19, /* /pin-controller/i2c0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux {2954885 /* 0x2d1685 */, 2922054 /* 0x2c9646 */}
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_IDX_0 2954885
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_IDX_1 2922054
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 0) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_LEN 2
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_drive_open_drain 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_enable 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_high 1
#define DT_N_S_pin_controller_S_i2c0_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/i2c1_default
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_default_PATH "/pin-controller/i2c1_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME "i2c1_default"
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_UNQUOTED i2c1_default
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_TOKEN i2c1_default
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME_UPPER_TOKEN I2C1_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_i2c1_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c1_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_NODELABEL(fn) fn(i2c1_default)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_i2c1_default_HASH XO1mymgcvFsuC9DhMfptRTCQBeKGbvb0Ib2nQh8oc7M

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_default_ORD 21
#define DT_N_S_pin_controller_S_i2c1_default_ORD_STR_SORTABLE 00021

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS \
	22, /* /pin-controller/i2c1_default/group1 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_default_EXISTS 1
#define DT_N_NODELABEL_i2c1_default DT_N_S_pin_controller_S_i2c1_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_default_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/i2c1_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_i2c1_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH "/pin-controller/i2c1_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/i2c1_default) identifier: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT DT_N_S_pin_controller_S_i2c1_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_HASH cUGMjaLJ_EMYBWGL8KTvzJXC89iE0MLZ6zre2oO0xVA

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD 22
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD_STR_SORTABLE 00022

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS \
	21, /* /pin-controller/i2c1_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux {3020584 /* 0x2e1728 */, 2987751 /* 0x2d96e7 */}
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_IDX_0 3020584
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_IDX_1 2987751
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 0) \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_LEN 2
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_drive_open_drain 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_enable 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_high 1
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/lcd_cam_default
 *
 * Node identifier: DT_N_S_pin_controller_S_lcd_cam_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_lcd_cam_default_PATH "/pin-controller/lcd_cam_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_lcd_cam_default_FULL_NAME "lcd_cam_default"
#define DT_N_S_pin_controller_S_lcd_cam_default_FULL_NAME_UNQUOTED lcd_cam_default
#define DT_N_S_pin_controller_S_lcd_cam_default_FULL_NAME_TOKEN lcd_cam_default
#define DT_N_S_pin_controller_S_lcd_cam_default_FULL_NAME_UPPER_TOKEN LCD_CAM_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_lcd_cam_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_lcd_cam_default_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_lcd_cam_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_NODELABEL(fn) fn(lcd_cam_default)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(lcd_cam_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_lcd_cam_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_lcd_cam_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_lcd_cam_default_HASH cc4nd9Q_bntppLXPFXNAdS9VMYoHotw76QqHsq3y4ag

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_lcd_cam_default_ORD 23
#define DT_N_S_pin_controller_S_lcd_cam_default_ORD_STR_SORTABLE 00023

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_lcd_cam_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_lcd_cam_default_SUPPORTS_ORDS \
	24, /* /pin-controller/lcd_cam_default/group1 */ \
	25, /* /pin-controller/lcd_cam_default/group2 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_lcd_cam_default_EXISTS 1
#define DT_N_NODELABEL_lcd_cam_default DT_N_S_pin_controller_S_lcd_cam_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_lcd_cam_default_REG_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_lcd_cam_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_lcd_cam_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/lcd_cam_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_lcd_cam_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_PATH "/pin-controller/lcd_cam_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/lcd_cam_default) identifier: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_PARENT DT_N_S_pin_controller_S_lcd_cam_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_HASH u4lv_6aO7I4Z5kQqBWuFZ892RNzEQD9zNw0xNRIyZDc

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_ORD 24
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_ORD_STR_SORTABLE 00024

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_REQUIRES_ORDS \
	23, /* /pin-controller/lcd_cam_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux {4915146 /* 0x4affca */}
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_IDX_0 4915146
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, pinmux, 0)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, pinmux, 0)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_LEN 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_enable 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_high 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/lcd_cam_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_lcd_cam_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_PATH "/pin-controller/lcd_cam_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FULL_NAME "group2"
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FULL_NAME_UNQUOTED group2
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FULL_NAME_TOKEN group2
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2

/* Node parent (/pin-controller/lcd_cam_default) identifier: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_PARENT DT_N_S_pin_controller_S_lcd_cam_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_HASH uk5XAHy9CB_Fe_ZvzvA8d1asntYcOssg_OgqIILy5Vc

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_ORD 25
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_ORD_STR_SORTABLE 00025

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_REQUIRES_ORDS \
	23, /* /pin-controller/lcd_cam_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux {16754214 /* 0xffa626 */, 16754095 /* 0xffa5af */, 16753997 /* 0xffa54d */, 16752975 /* 0xffa14f */, 16753041 /* 0xffa191 */, 16753106 /* 0xffa1d2 */, 16753168 /* 0xffa210 */, 16753230 /* 0xffa24e */, 16753292 /* 0xffa28c */, 16753355 /* 0xffa2cb */, 16753456 /* 0xffa330 */}
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_0 16754214
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_1 16754095
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_2_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_2 16753997
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_3_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_3 16752975
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_4_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_4 16753041
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_5_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_5 16753106
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_6_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_6 16753168
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_7_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_7 16753230
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_8_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_8 16753292
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_9_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_9 16753355
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_10_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_IDX_10 16753456
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 0) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 1) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 2) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 3) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 4) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 5) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 6) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 7) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 8) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 9) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 10)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 1) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 2) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 3) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 4) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 5) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 6) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 7) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 8) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 9) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 10)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 1, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 2, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 3, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 4, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 5, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 6, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 7, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 8, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 9, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 10, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 7, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 8, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 9, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, pinmux, 10, __VA_ARGS__)
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_LEN 11
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_disable 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_input_enable 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_enable 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_low 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_high 0
#define DT_N_S_pin_controller_S_lcd_cam_default_S_group2_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/spim2_default
 *
 * Node identifier: DT_N_S_pin_controller_S_spim2_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spim2_default_PATH "/pin-controller/spim2_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spim2_default_FULL_NAME "spim2_default"
#define DT_N_S_pin_controller_S_spim2_default_FULL_NAME_UNQUOTED spim2_default
#define DT_N_S_pin_controller_S_spim2_default_FULL_NAME_TOKEN spim2_default
#define DT_N_S_pin_controller_S_spim2_default_FULL_NAME_UPPER_TOKEN SPIM2_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_spim2_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spim2_default_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spim2_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_NODELABEL(fn) fn(spim2_default)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(spim2_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spim2_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_spim2_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) fn(DT_N_S_pin_controller_S_spim2_default_S_group2)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default_S_group2)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) fn(DT_N_S_pin_controller_S_spim2_default_S_group2)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default_S_group2)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_spim2_default_HASH yQ9p_zZ49maZmOnOVWRekcc6Lo5_twi_vyjzjg0jqIA

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spim2_default_ORD 26
#define DT_N_S_pin_controller_S_spim2_default_ORD_STR_SORTABLE 00026

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spim2_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spim2_default_SUPPORTS_ORDS \
	27, /* /pin-controller/spim2_default/group1 */ \
	28, /* /pin-controller/spim2_default/group2 */ \
	103, /* /soc/spi@60024000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spim2_default_EXISTS 1
#define DT_N_NODELABEL_spim2_default DT_N_S_pin_controller_S_spim2_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spim2_default_REG_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spim2_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spim2_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spim2_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spim2_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/spim2_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_spim2_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_PATH "/pin-controller/spim2_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/spim2_default) identifier: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_PARENT DT_N_S_pin_controller_S_spim2_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_HASH p70n6PMDj1QKr_sTZSVNVgh8FWjeQJk5mPn3eq_6lJ0

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_ORD 27
#define DT_N_S_pin_controller_S_spim2_default_S_group1_ORD_STR_SORTABLE 00027

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_REQUIRES_ORDS \
	26, /* /pin-controller/spim2_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux {16750984 /* 0xff9988 */, 3342279 /* 0x32ffc7 */}
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_IDX_0 16750984
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_IDX_1 3342279
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 0) \
	fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_spim2_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_LEN 2
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_enable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_high 0
#define DT_N_S_pin_controller_S_spim2_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/spim2_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_spim2_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_PATH "/pin-controller/spim2_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FULL_NAME "group2"
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FULL_NAME_UNQUOTED group2
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FULL_NAME_TOKEN group2
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2

/* Node parent (/pin-controller/spim2_default) identifier: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_PARENT DT_N_S_pin_controller_S_spim2_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_HASH 8QjmDqnyBap6vP7Vx84h2_Dt9Pvj6PnRYgLNX1RakyE

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_ORD 28
#define DT_N_S_pin_controller_S_spim2_default_S_group2_ORD_STR_SORTABLE 00028

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_REQUIRES_ORDS \
	26, /* /pin-controller/spim2_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_spim2_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux {3407817 /* 0x33ffc9 */}
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_IDX_0 3407817
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, pinmux, 0)
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, pinmux, 0)
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_LEN 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_input_enable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_enable 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_low 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_high 0
#define DT_N_S_pin_controller_S_spim2_default_S_group2_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/twai_default
 *
 * Node identifier: DT_N_S_pin_controller_S_twai_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_twai_default_PATH "/pin-controller/twai_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_twai_default_FULL_NAME "twai_default"
#define DT_N_S_pin_controller_S_twai_default_FULL_NAME_UNQUOTED twai_default
#define DT_N_S_pin_controller_S_twai_default_FULL_NAME_TOKEN twai_default
#define DT_N_S_pin_controller_S_twai_default_FULL_NAME_UPPER_TOKEN TWAI_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_twai_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_twai_default_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_twai_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_twai_default_FOREACH_NODELABEL(fn) fn(twai_default)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(twai_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_twai_default_CHILD_NUM 1
#define DT_N_S_pin_controller_S_twai_default_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_twai_default_S_group1)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_twai_default_S_group1)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_twai_default_S_group1)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_twai_default_S_group1)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_twai_default_HASH cEr2u_JuEoEHCq3kPvei4M__t8osI1CvuALLllai_uU

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_twai_default_ORD 29
#define DT_N_S_pin_controller_S_twai_default_ORD_STR_SORTABLE 00029

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_twai_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_twai_default_SUPPORTS_ORDS \
	30, /* /pin-controller/twai_default/group1 */ \
	38, /* /soc/can@6002b000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_twai_default_EXISTS 1
#define DT_N_NODELABEL_twai_default DT_N_S_pin_controller_S_twai_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_twai_default_REG_NUM 0
#define DT_N_S_pin_controller_S_twai_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_twai_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_twai_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_twai_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_twai_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_twai_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_twai_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_twai_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_twai_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_twai_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/twai_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_twai_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_PATH "/pin-controller/twai_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_twai_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_twai_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_twai_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/twai_default) identifier: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_PARENT DT_N_S_pin_controller_S_twai_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_twai_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_twai_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_HASH _ZgFg5F7NoK6z5R4_vAnmRSqhaS7xGTIFjL00CcXRSE

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_ORD 30
#define DT_N_S_pin_controller_S_twai_default_S_group1_ORD_STR_SORTABLE 00030

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_REQUIRES_ORDS \
	29, /* /pin-controller/twai_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_twai_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux {3833795 /* 0x3a7fc3 */, 16751876 /* 0xff9d04 */}
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_IDX_0 3833795
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_IDX_1_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_IDX_1 16751876
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 0) \
	fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 1)
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 0, __VA_ARGS__) \
	fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_pin_controller_S_twai_default_S_group1, pinmux, 1, __VA_ARGS__)
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_LEN 2
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_enable 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_high 0
#define DT_N_S_pin_controller_S_twai_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_default
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_PATH "/pin-controller/uart0_default"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME "uart0_default"
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_UNQUOTED uart0_default
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_TOKEN uart0_default
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME_UPPER_TOKEN UART0_DEFAULT

/* Node parent (/pin-controller) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_PARENT DT_N_S_pin_controller

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart0_default_NODELABEL_NUM 1
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_NODELABEL(fn) fn(uart0_default)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0_default, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM 2
#define DT_N_S_pin_controller_S_uart0_default_CHILD_NUM_STATUS_OKAY 2
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_pin_controller_S_uart0_default_HASH hpPoQq5QYEcDym1g2JBVllTKxA90m_i7KnAuJScDL4o

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_ORD 31
#define DT_N_S_pin_controller_S_uart0_default_ORD_STR_SORTABLE 00031

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS \
	18, /* /pin-controller */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS \
	32, /* /pin-controller/uart0_default/group1 */ \
	33, /* /pin-controller/uart0_default/group2 */ \
	64, /* /soc/uart@60000000 */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_EXISTS 1
#define DT_N_NODELABEL_uart0_default DT_N_S_pin_controller_S_uart0_default

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM 0

/* (No generic property macros) */

/*
 * Devicetree node: /pin-controller/uart0_default/group1
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group1
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH "/pin-controller/uart0_default/group1"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME "group1"
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_UNQUOTED group1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_TOKEN group1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME_UPPER_TOKEN GROUP1

/* Node parent (/pin-controller/uart0_default) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT DT_N_S_pin_controller_S_uart0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_HASH mw9A94JnX0K15LdzaqSiBYHstgeiBk__IFPWTJ90zX0

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD 32
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD_STR_SORTABLE 00032

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS \
	31, /* /pin-controller/uart0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux {425963 /* 0x67feb */}
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_IDX_0 425963
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, pinmux, 0)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, pinmux, 0)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_LEN 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_input_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_low 0
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_high 1
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_output_high_EXISTS 1

/*
 * Devicetree node: /pin-controller/uart0_default/group2
 *
 * Node identifier: DT_N_S_pin_controller_S_uart0_default_S_group2
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH "/pin-controller/uart0_default/group2"

/* Node's name with unit-address: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME "group2"
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_UNQUOTED group2
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_TOKEN group2
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME_UPPER_TOKEN GROUP2

/* Node parent (/pin-controller/uart0_default) identifier: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT DT_N_S_pin_controller_S_uart0_default

/* Node's index in its parent's list of children: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_NODELABEL_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_NODELABEL(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_ANCESTOR(fn) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_HASH OhplDHWYl94QPNbqB4nVbAksIsz36XFx3_uS1MnAXRo

/* Node's dependency ordinal: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD 33
#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD_STR_SORTABLE 00033

/* Ordinals for what this node depends on directly: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS \
	31, /* /pin-controller/uart0_default */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS 1

/* Macros for properties that are special in the specification: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_REG(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn) 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_LEVEL 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux {16745260 /* 0xff832c */}
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_IDX_0_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_IDX_0 16745260
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_FOREACH_PROP_ELEM(fn) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, pinmux, 0)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, pinmux, 0)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, pinmux, 0, __VA_ARGS__)
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_LEN 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_pinmux_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_sleep_hold_en 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_sleep_hold_en_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_drive_push_pull 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_drive_push_pull_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_drive_open_drain 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_drive_open_drain_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_input_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_input_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_enable 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_enable_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_low 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_low_EXISTS 1
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_high 0
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_output_high_EXISTS 1

/*
 * Devicetree node: /clock
 *
 * Node identifier: DT_N_S_clock
 *
 * Binding (compatible = espressif,esp32-clock):
 *   $ZEPHYR_BASE/dts/bindings/clock/espressif,esp32-clock.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_clock_PATH "/clock"

/* Node's name with unit-address: */
#define DT_N_S_clock_FULL_NAME "clock"
#define DT_N_S_clock_FULL_NAME_UNQUOTED clock
#define DT_N_S_clock_FULL_NAME_TOKEN clock
#define DT_N_S_clock_FULL_NAME_UPPER_TOKEN CLOCK

/* Node parent (/) identifier: */
#define DT_N_S_clock_PARENT DT_N

/* Node's index in its parent's list of children: */
#define DT_N_S_clock_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_clock_NODELABEL_NUM 1
#define DT_N_S_clock_FOREACH_NODELABEL(fn) fn(clock)
#define DT_N_S_clock_FOREACH_NODELABEL_VARGS(fn, ...) fn(clock, __VA_ARGS__)
#define DT_N_S_clock_FOREACH_ANCESTOR(fn) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_clock_CHILD_NUM 0
#define DT_N_S_clock_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_clock_FOREACH_CHILD(fn) 
#define DT_N_S_clock_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_clock_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_clock_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clock_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_clock_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_clock_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_clock_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_clock_HASH QnKLwDxmAK_PaPqjnffzth94QNFQAD6J185NwWdLjGI

/* Node's dependency ordinal: */
#define DT_N_S_clock_ORD 34
#define DT_N_S_clock_ORD_STR_SORTABLE 00034

/* Ordinals for what this node depends on directly: */
#define DT_N_S_clock_REQUIRES_ORDS \
	0, /* / */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_clock_SUPPORTS_ORDS \
	35, /* /soc/adc@60040000 */ \
	36, /* /soc/adc@60040004 */ \
	37, /* /soc/aes@6003a000 */ \
	38, /* /soc/can@6002b000 */ \
	40, /* /soc/i2c@60013000 */ \
	41, /* /soc/i2c@60027000 */ \
	42, /* /soc/dma@6003f000 */ \
	43, /* /soc/i2s@6000f000 */ \
	44, /* /soc/i2s@6002d000 */ \
	47, /* /soc/ledc@60019000 */ \
	49, /* /soc/mcpwm@6001e000 */ \
	50, /* /soc/mcpwm@6002c000 */ \
	58, /* /soc/pcnt@60017000 */ \
	59, /* /soc/rtc_timer@60008004 */ \
	60, /* /soc/sha@6003b000 */ \
	61, /* /soc/spi@60025000 */ \
	63, /* /soc/trng@6003507c */ \
	64, /* /soc/uart@60000000 */ \
	65, /* /soc/uart@60010000 */ \
	66, /* /soc/uart@6002e000 */ \
	67, /* /soc/uart@60038000 */ \
	68, /* /soc/usb_otg@60080000 */ \
	69, /* /soc/watchdog@6001f048 */ \
	70, /* /soc/watchdog@60020048 */ \
	71, /* /soc/xt_wdt@60021004 */ \
	72, /* /soc/counter@6001f000 */ \
	74, /* /soc/counter@6001f024 */ \
	76, /* /soc/counter@60020000 */ \
	78, /* /soc/counter@60020024 */ \
	95, /* /soc/lcd_cam@60041000 */ \
	100, /* /soc/sdhc@60028000 */ \
	103, /* /soc/spi@60024000 */

/* Existence and alternate IDs: */
#define DT_N_S_clock_EXISTS 1
#define DT_N_INST_0_espressif_esp32_clock DT_N_S_clock
#define DT_N_NODELABEL_clock              DT_N_S_clock

/* Macros for properties that are special in the specification: */
#define DT_N_S_clock_REG_NUM 0
#define DT_N_S_clock_FOREACH_REG(fn) 
#define DT_N_S_clock_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_clock_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_clock_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_clock_RANGES_NUM 0
#define DT_N_S_clock_FOREACH_RANGE(fn) 
#define DT_N_S_clock_IRQ_NUM 0
#define DT_N_S_clock_IRQ_LEVEL 0
#define DT_N_S_clock_COMPAT_MATCHES_espressif_esp32_clock 1
#define DT_N_S_clock_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_clock_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_clock_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_clock_COMPAT_MODEL_IDX_0 "esp32-clock"
#define DT_N_S_clock_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_clock_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_clock_P_fast_clk_src 1
#define DT_N_S_clock_P_fast_clk_src_IDX_0_ENUM_IDX 1
#define DT_N_S_clock_P_fast_clk_src_IDX_0_EXISTS 1
#define DT_N_S_clock_P_fast_clk_src_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_clock_P_fast_clk_src_ENUM_VAL_1_EXISTS 1
#define DT_N_S_clock_P_fast_clk_src_EXISTS 1
#define DT_N_S_clock_P_slow_clk_src 0
#define DT_N_S_clock_P_slow_clk_src_IDX_0_ENUM_IDX 0
#define DT_N_S_clock_P_slow_clk_src_IDX_0_EXISTS 1
#define DT_N_S_clock_P_slow_clk_src_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_clock_P_slow_clk_src_ENUM_VAL_0_EXISTS 1
#define DT_N_S_clock_P_slow_clk_src_EXISTS 1

/*
 * Devicetree node: /soc/adc@60040000
 *
 * Node identifier: DT_N_S_soc_S_adc_60040000
 *
 * Binding (compatible = espressif,esp32-adc):
 *   $ZEPHYR_BASE/dts/bindings/adc/espressif,esp32-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_60040000_PATH "/soc/adc@60040000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_60040000_FULL_NAME "adc@60040000"
#define DT_N_S_soc_S_adc_60040000_FULL_NAME_UNQUOTED adc@60040000
#define DT_N_S_soc_S_adc_60040000_FULL_NAME_TOKEN adc_60040000
#define DT_N_S_soc_S_adc_60040000_FULL_NAME_UPPER_TOKEN ADC_60040000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_60040000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_60040000_CHILD_IDX 27

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_60040000_NODELABEL_NUM 2
#define DT_N_S_soc_S_adc_60040000_FOREACH_NODELABEL(fn) fn(adc0) fn(xiao_adc)
#define DT_N_S_soc_S_adc_60040000_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc0, __VA_ARGS__) fn(xiao_adc, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_60040000_CHILD_NUM 0
#define DT_N_S_soc_S_adc_60040000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_60040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_60040000_HASH kIFkITTsWHxDzqiccZgKpCp6UYxr1Xa1kpKjb_sgujM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_60040000_ORD 35
#define DT_N_S_soc_S_adc_60040000_ORD_STR_SORTABLE 00035

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_60040000_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_60040000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_60040000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_adc DT_N_S_soc_S_adc_60040000
#define DT_N_NODELABEL_adc0             DT_N_S_soc_S_adc_60040000
#define DT_N_NODELABEL_xiao_adc         DT_N_S_soc_S_adc_60040000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_60040000_REG_NUM 1
#define DT_N_S_soc_S_adc_60040000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_REG_IDX_0_VAL_ADDRESS 1610874880 /* 0x60040000 */
#define DT_N_S_soc_S_adc_60040000_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_adc_60040000_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_60040000, 0)
#define DT_N_S_soc_S_adc_60040000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040000, 0)
#define DT_N_S_soc_S_adc_60040000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_RANGES_NUM 0
#define DT_N_S_soc_S_adc_60040000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_60040000_IRQ_NUM 0
#define DT_N_S_soc_S_adc_60040000_IRQ_LEVEL 0
#define DT_N_S_soc_S_adc_60040000_COMPAT_MATCHES_espressif_esp32_adc 1
#define DT_N_S_soc_S_adc_60040000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_adc_60040000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_COMPAT_MODEL_IDX_0 "esp32-adc"
#define DT_N_S_soc_S_adc_60040000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_60040000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_60040000_P_unit 1
#define DT_N_S_soc_S_adc_60040000_P_unit_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_channel_count 10
#define DT_N_S_soc_S_adc_60040000_P_channel_count_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_status "disabled"
#define DT_N_S_soc_S_adc_60040000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_60040000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_60040000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_60040000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_60040000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_60040000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040000, status, 0)
#define DT_N_S_soc_S_adc_60040000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040000, status, 0)
#define DT_N_S_soc_S_adc_60040000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_status_LEN 1
#define DT_N_S_soc_S_adc_60040000_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_compatible {"espressif,esp32-adc"}
#define DT_N_S_soc_S_adc_60040000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_compatible_IDX_0 "espressif,esp32-adc"
#define DT_N_S_soc_S_adc_60040000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-adc
#define DT_N_S_soc_S_adc_60040000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_adc
#define DT_N_S_soc_S_adc_60040000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_ADC
#define DT_N_S_soc_S_adc_60040000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040000, compatible, 0)
#define DT_N_S_soc_S_adc_60040000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040000, compatible, 0)
#define DT_N_S_soc_S_adc_60040000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_compatible_LEN 1
#define DT_N_S_soc_S_adc_60040000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_reg {1610874880 /* 0x60040000 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_adc_60040000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_reg_IDX_0 1610874880
#define DT_N_S_soc_S_adc_60040000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_reg_IDX_1 4
#define DT_N_S_soc_S_adc_60040000_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_VAL_offset 128
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_60040000, clocks, 0, offset)
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040000, clocks, 0, offset)
#define DT_N_S_soc_S_adc_60040000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_adc_60040000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040000, clocks, 0)
#define DT_N_S_soc_S_adc_60040000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040000, clocks, 0)
#define DT_N_S_soc_S_adc_60040000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040000_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_60040000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_60040000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_wakeup_source 0
#define DT_N_S_soc_S_adc_60040000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_60040000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_60040000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/adc@60040004
 *
 * Node identifier: DT_N_S_soc_S_adc_60040004
 *
 * Binding (compatible = espressif,esp32-adc):
 *   $ZEPHYR_BASE/dts/bindings/adc/espressif,esp32-adc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_adc_60040004_PATH "/soc/adc@60040004"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_adc_60040004_FULL_NAME "adc@60040004"
#define DT_N_S_soc_S_adc_60040004_FULL_NAME_UNQUOTED adc@60040004
#define DT_N_S_soc_S_adc_60040004_FULL_NAME_TOKEN adc_60040004
#define DT_N_S_soc_S_adc_60040004_FULL_NAME_UPPER_TOKEN ADC_60040004

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_adc_60040004_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_adc_60040004_CHILD_IDX 28

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_adc_60040004_NODELABEL_NUM 1
#define DT_N_S_soc_S_adc_60040004_FOREACH_NODELABEL(fn) fn(adc1)
#define DT_N_S_soc_S_adc_60040004_FOREACH_NODELABEL_VARGS(fn, ...) fn(adc1, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_adc_60040004_CHILD_NUM 0
#define DT_N_S_soc_S_adc_60040004_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_adc_60040004_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_adc_60040004_HASH dFVLk3VrlMmJwBVWr8Jb6bwSyE0wZMGrTZeOcWrrwus

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_adc_60040004_ORD 36
#define DT_N_S_soc_S_adc_60040004_ORD_STR_SORTABLE 00036

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_adc_60040004_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_adc_60040004_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_adc_60040004_EXISTS 1
#define DT_N_INST_1_espressif_esp32_adc DT_N_S_soc_S_adc_60040004
#define DT_N_NODELABEL_adc1             DT_N_S_soc_S_adc_60040004

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_adc_60040004_REG_NUM 1
#define DT_N_S_soc_S_adc_60040004_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_REG_IDX_0_VAL_ADDRESS 1610874884 /* 0x60040004 */
#define DT_N_S_soc_S_adc_60040004_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_adc_60040004_FOREACH_REG(fn) fn(DT_N_S_soc_S_adc_60040004, 0)
#define DT_N_S_soc_S_adc_60040004_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040004, 0)
#define DT_N_S_soc_S_adc_60040004_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_RANGES_NUM 0
#define DT_N_S_soc_S_adc_60040004_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_adc_60040004_IRQ_NUM 0
#define DT_N_S_soc_S_adc_60040004_IRQ_LEVEL 0
#define DT_N_S_soc_S_adc_60040004_COMPAT_MATCHES_espressif_esp32_adc 1
#define DT_N_S_soc_S_adc_60040004_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_adc_60040004_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_COMPAT_MODEL_IDX_0 "esp32-adc"
#define DT_N_S_soc_S_adc_60040004_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_adc_60040004_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_adc_60040004_P_unit 2
#define DT_N_S_soc_S_adc_60040004_P_unit_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_channel_count 10
#define DT_N_S_soc_S_adc_60040004_P_channel_count_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_status "disabled"
#define DT_N_S_soc_S_adc_60040004_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_adc_60040004_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_adc_60040004_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_adc_60040004_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_adc_60040004_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_adc_60040004_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040004, status, 0)
#define DT_N_S_soc_S_adc_60040004_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040004, status, 0)
#define DT_N_S_soc_S_adc_60040004_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_status_LEN 1
#define DT_N_S_soc_S_adc_60040004_P_status_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_compatible {"espressif,esp32-adc"}
#define DT_N_S_soc_S_adc_60040004_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_compatible_IDX_0 "espressif,esp32-adc"
#define DT_N_S_soc_S_adc_60040004_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-adc
#define DT_N_S_soc_S_adc_60040004_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_adc
#define DT_N_S_soc_S_adc_60040004_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_ADC
#define DT_N_S_soc_S_adc_60040004_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040004, compatible, 0)
#define DT_N_S_soc_S_adc_60040004_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040004, compatible, 0)
#define DT_N_S_soc_S_adc_60040004_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_compatible_LEN 1
#define DT_N_S_soc_S_adc_60040004_P_compatible_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_reg {1610874884 /* 0x60040004 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_adc_60040004_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_reg_IDX_0 1610874884
#define DT_N_S_soc_S_adc_60040004_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_reg_IDX_1 4
#define DT_N_S_soc_S_adc_60040004_P_reg_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_VAL_offset 128
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_adc_60040004, clocks, 0, offset)
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040004, clocks, 0, offset)
#define DT_N_S_soc_S_adc_60040004_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_adc_60040004_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_60040004, clocks, 0)
#define DT_N_S_soc_S_adc_60040004_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_60040004, clocks, 0)
#define DT_N_S_soc_S_adc_60040004_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_60040004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_60040004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_adc_60040004_P_clocks_LEN 1
#define DT_N_S_soc_S_adc_60040004_P_clocks_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_adc_60040004_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_wakeup_source 0
#define DT_N_S_soc_S_adc_60040004_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_adc_60040004_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_adc_60040004_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/aes@6003a000
 *
 * Node identifier: DT_N_S_soc_S_aes_6003a000
 *
 * Binding (compatible = espressif,esp32-aes):
 *   $ZEPHYR_BASE/dts/bindings/crypto/espressif,esp32-aes.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_aes_6003a000_PATH "/soc/aes@6003a000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_aes_6003a000_FULL_NAME "aes@6003a000"
#define DT_N_S_soc_S_aes_6003a000_FULL_NAME_UNQUOTED aes@6003a000
#define DT_N_S_soc_S_aes_6003a000_FULL_NAME_TOKEN aes_6003a000
#define DT_N_S_soc_S_aes_6003a000_FULL_NAME_UPPER_TOKEN AES_6003A000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_aes_6003a000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_aes_6003a000_CHILD_IDX 47

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_aes_6003a000_NODELABEL_NUM 1
#define DT_N_S_soc_S_aes_6003a000_FOREACH_NODELABEL(fn) fn(aes)
#define DT_N_S_soc_S_aes_6003a000_FOREACH_NODELABEL_VARGS(fn, ...) fn(aes, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_aes_6003a000_CHILD_NUM 0
#define DT_N_S_soc_S_aes_6003a000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_aes_6003a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_aes_6003a000_HASH MFS__ZEns9tRDXy96omnCTc6M43c63zQYT_5yZPvHEM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_aes_6003a000_ORD 37
#define DT_N_S_soc_S_aes_6003a000_ORD_STR_SORTABLE 00037

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_aes_6003a000_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_aes_6003a000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_aes_6003a000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_aes DT_N_S_soc_S_aes_6003a000
#define DT_N_NODELABEL_aes              DT_N_S_soc_S_aes_6003a000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_aes_6003a000_REG_NUM 1
#define DT_N_S_soc_S_aes_6003a000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_REG_IDX_0_VAL_ADDRESS 1610850304 /* 0x6003a000 */
#define DT_N_S_soc_S_aes_6003a000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_aes_6003a000_FOREACH_REG(fn) fn(DT_N_S_soc_S_aes_6003a000, 0)
#define DT_N_S_soc_S_aes_6003a000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_aes_6003a000, 0)
#define DT_N_S_soc_S_aes_6003a000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_aes_6003a000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_aes_6003a000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_RANGES_NUM 0
#define DT_N_S_soc_S_aes_6003a000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_aes_6003a000_IRQ_NUM 0
#define DT_N_S_soc_S_aes_6003a000_IRQ_LEVEL 0
#define DT_N_S_soc_S_aes_6003a000_COMPAT_MATCHES_espressif_esp32_aes 1
#define DT_N_S_soc_S_aes_6003a000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_aes_6003a000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_COMPAT_MODEL_IDX_0 "esp32-aes"
#define DT_N_S_soc_S_aes_6003a000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_aes_6003a000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_aes_6003a000_P_status "okay"
#define DT_N_S_soc_S_aes_6003a000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_aes_6003a000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_aes_6003a000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_aes_6003a000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_aes_6003a000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_aes_6003a000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aes_6003a000, status, 0)
#define DT_N_S_soc_S_aes_6003a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_aes_6003a000, status, 0)
#define DT_N_S_soc_S_aes_6003a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aes_6003a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_aes_6003a000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_status_LEN 1
#define DT_N_S_soc_S_aes_6003a000_P_status_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_compatible {"espressif,esp32-aes"}
#define DT_N_S_soc_S_aes_6003a000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_compatible_IDX_0 "espressif,esp32-aes"
#define DT_N_S_soc_S_aes_6003a000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-aes
#define DT_N_S_soc_S_aes_6003a000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_aes
#define DT_N_S_soc_S_aes_6003a000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_AES
#define DT_N_S_soc_S_aes_6003a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aes_6003a000, compatible, 0)
#define DT_N_S_soc_S_aes_6003a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_aes_6003a000, compatible, 0)
#define DT_N_S_soc_S_aes_6003a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aes_6003a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_aes_6003a000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_compatible_LEN 1
#define DT_N_S_soc_S_aes_6003a000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_reg {1610850304 /* 0x6003a000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_aes_6003a000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_reg_IDX_0 1610850304
#define DT_N_S_soc_S_aes_6003a000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_aes_6003a000_P_reg_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_VAL_offset 121
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0, offset)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0, offset)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_aes_6003a000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_aes_6003a000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_aes_6003a000_P_clocks_LEN 1
#define DT_N_S_soc_S_aes_6003a000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_aes_6003a000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_wakeup_source 0
#define DT_N_S_soc_S_aes_6003a000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_aes_6003a000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_aes_6003a000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/can@6002b000
 *
 * Node identifier: DT_N_S_soc_S_can_6002b000
 *
 * Binding (compatible = espressif,esp32-twai):
 *   $ZEPHYR_BASE/dts/bindings/can/espressif,esp32-twai.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_can_6002b000_PATH "/soc/can@6002b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_can_6002b000_FULL_NAME "can@6002b000"
#define DT_N_S_soc_S_can_6002b000_FULL_NAME_UNQUOTED can@6002b000
#define DT_N_S_soc_S_can_6002b000_FULL_NAME_TOKEN can_6002b000
#define DT_N_S_soc_S_can_6002b000_FULL_NAME_UPPER_TOKEN CAN_6002B000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_can_6002b000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_can_6002b000_CHILD_IDX 29

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_can_6002b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_can_6002b000_FOREACH_NODELABEL(fn) fn(twai)
#define DT_N_S_soc_S_can_6002b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(twai, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_can_6002b000_CHILD_NUM 0
#define DT_N_S_soc_S_can_6002b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_can_6002b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_can_6002b000_HASH 5r5gdCmTNDc_BaL_yCWZJGUz9pqM5G_LAQAzeh6ftoA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_can_6002b000_ORD 38
#define DT_N_S_soc_S_can_6002b000_ORD_STR_SORTABLE 00038

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_can_6002b000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	29, /* /pin-controller/twai_default */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_can_6002b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_can_6002b000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_twai DT_N_S_soc_S_can_6002b000
#define DT_N_NODELABEL_twai              DT_N_S_soc_S_can_6002b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_can_6002b000_REG_NUM 1
#define DT_N_S_soc_S_can_6002b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_REG_IDX_0_VAL_ADDRESS 1610788864 /* 0x6002b000 */
#define DT_N_S_soc_S_can_6002b000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_can_6002b000_FOREACH_REG(fn) fn(DT_N_S_soc_S_can_6002b000, 0)
#define DT_N_S_soc_S_can_6002b000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, 0)
#define DT_N_S_soc_S_can_6002b000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_RANGES_NUM 0
#define DT_N_S_soc_S_can_6002b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_can_6002b000_IRQ_NUM 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_irq 37
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_can_6002b000_IRQ_LEVEL 1
#define DT_N_S_soc_S_can_6002b000_COMPAT_MATCHES_espressif_esp32_twai 1
#define DT_N_S_soc_S_can_6002b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_can_6002b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_COMPAT_MODEL_IDX_0 "esp32-twai"
#define DT_N_S_soc_S_can_6002b000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_can_6002b000_PINCTRL_NUM 1
#define DT_N_S_soc_S_can_6002b000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_can_6002b000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_can_6002b000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_can_6002b000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_twai_default

/* Generic property macros: */
#define DT_N_S_soc_S_can_6002b000_P_reg {1610788864 /* 0x6002b000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_can_6002b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_reg_IDX_0 1610788864
#define DT_N_S_soc_S_can_6002b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_can_6002b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupts {37 /* 0x25 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_0 37
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_can_6002b000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_VAL_offset 118
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_can_6002b000, clocks, 0, offset)
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, clocks, 0, offset)
#define DT_N_S_soc_S_can_6002b000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_can_6002b000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, clocks, 0)
#define DT_N_S_soc_S_can_6002b000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, clocks, 0)
#define DT_N_S_soc_S_can_6002b000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_clocks_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_twai_default
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_twai_default
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, pinctrl_0, 0)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, pinctrl_0, 0)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, pinctrl_names, 0)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, pinctrl_names, 0)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_status "disabled"
#define DT_N_S_soc_S_can_6002b000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_can_6002b000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_can_6002b000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_can_6002b000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_can_6002b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_can_6002b000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, status, 0)
#define DT_N_S_soc_S_can_6002b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, status, 0)
#define DT_N_S_soc_S_can_6002b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_status_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_status_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_compatible {"espressif,esp32-twai"}
#define DT_N_S_soc_S_can_6002b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_compatible_IDX_0 "espressif,esp32-twai"
#define DT_N_S_soc_S_can_6002b000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-twai
#define DT_N_S_soc_S_can_6002b000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_twai
#define DT_N_S_soc_S_can_6002b000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TWAI
#define DT_N_S_soc_S_can_6002b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, compatible, 0)
#define DT_N_S_soc_S_can_6002b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, compatible, 0)
#define DT_N_S_soc_S_can_6002b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_compatible_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_6002b000, interrupt_parent, 0)
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_6002b000, interrupt_parent, 0)
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_6002b000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_6002b000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_can_6002b000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_can_6002b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_wakeup_source 0
#define DT_N_S_soc_S_can_6002b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_can_6002b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_can_6002b000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/coretemp@60008800
 *
 * Node identifier: DT_N_S_soc_S_coretemp_60008800
 *
 * Binding (compatible = espressif,esp32-temp):
 *   $ZEPHYR_BASE/dts/bindings/sensor/espressif,esp32-temp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_coretemp_60008800_PATH "/soc/coretemp@60008800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_coretemp_60008800_FULL_NAME "coretemp@60008800"
#define DT_N_S_soc_S_coretemp_60008800_FULL_NAME_UNQUOTED coretemp@60008800
#define DT_N_S_soc_S_coretemp_60008800_FULL_NAME_TOKEN coretemp_60008800
#define DT_N_S_soc_S_coretemp_60008800_FULL_NAME_UPPER_TOKEN CORETEMP_60008800

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_coretemp_60008800_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_coretemp_60008800_CHILD_IDX 26

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_coretemp_60008800_NODELABEL_NUM 1
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_NODELABEL(fn) fn(coretemp)
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_NODELABEL_VARGS(fn, ...) fn(coretemp, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_coretemp_60008800_CHILD_NUM 0
#define DT_N_S_soc_S_coretemp_60008800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_coretemp_60008800_HASH s570n_MdF8JSOwZbhQjCHHlLF8TLPdTfxDKC5TQAz0Y

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_coretemp_60008800_ORD 39
#define DT_N_S_soc_S_coretemp_60008800_ORD_STR_SORTABLE 00039

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_coretemp_60008800_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_coretemp_60008800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_coretemp_60008800_EXISTS 1
#define DT_N_ALIAS_die_temp0             DT_N_S_soc_S_coretemp_60008800
#define DT_N_INST_0_espressif_esp32_temp DT_N_S_soc_S_coretemp_60008800
#define DT_N_NODELABEL_coretemp          DT_N_S_soc_S_coretemp_60008800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_coretemp_60008800_REG_NUM 1
#define DT_N_S_soc_S_coretemp_60008800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_REG_IDX_0_VAL_ADDRESS 1610647552 /* 0x60008800 */
#define DT_N_S_soc_S_coretemp_60008800_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_REG(fn) fn(DT_N_S_soc_S_coretemp_60008800, 0)
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_coretemp_60008800, 0)
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_coretemp_60008800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_coretemp_60008800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_RANGES_NUM 0
#define DT_N_S_soc_S_coretemp_60008800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_coretemp_60008800_IRQ_NUM 0
#define DT_N_S_soc_S_coretemp_60008800_IRQ_LEVEL 0
#define DT_N_S_soc_S_coretemp_60008800_COMPAT_MATCHES_espressif_esp32_temp 1
#define DT_N_S_soc_S_coretemp_60008800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_coretemp_60008800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_COMPAT_MODEL_IDX_0 "esp32-temp"
#define DT_N_S_soc_S_coretemp_60008800_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_coretemp_60008800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_coretemp_60008800_P_range_min -10
#define DT_N_S_soc_S_coretemp_60008800_P_range_min_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_range_max 80
#define DT_N_S_soc_S_coretemp_60008800_P_range_max_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name "coretemp"
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_STRING_UNQUOTED coretemp
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_STRING_TOKEN coretemp
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_STRING_UPPER_TOKEN CORETEMP
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_IDX_0 "coretemp"
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_coretemp_60008800, friendly_name, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_coretemp_60008800, friendly_name, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_coretemp_60008800, friendly_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_coretemp_60008800, friendly_name, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_LEN 1
#define DT_N_S_soc_S_coretemp_60008800_P_friendly_name_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_status "disabled"
#define DT_N_S_soc_S_coretemp_60008800_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_coretemp_60008800_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_coretemp_60008800_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_coretemp_60008800_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_coretemp_60008800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_coretemp_60008800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_coretemp_60008800, status, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_coretemp_60008800, status, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_coretemp_60008800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_coretemp_60008800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_status_LEN 1
#define DT_N_S_soc_S_coretemp_60008800_P_status_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_compatible {"espressif,esp32-temp"}
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_IDX_0 "espressif,esp32-temp"
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-temp
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_temp
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TEMP
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_coretemp_60008800, compatible, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_coretemp_60008800, compatible, 0)
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_coretemp_60008800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_coretemp_60008800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_LEN 1
#define DT_N_S_soc_S_coretemp_60008800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_reg {1610647552 /* 0x60008800 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_coretemp_60008800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_reg_IDX_0 1610647552
#define DT_N_S_soc_S_coretemp_60008800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_reg_IDX_1 4
#define DT_N_S_soc_S_coretemp_60008800_P_reg_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_coretemp_60008800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_wakeup_source 0
#define DT_N_S_soc_S_coretemp_60008800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_coretemp_60008800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_coretemp_60008800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2c@60013000
 *
 * Node identifier: DT_N_S_soc_S_i2c_60013000
 *
 * Binding (compatible = espressif,esp32-i2c):
 *   $ZEPHYR_BASE/dts/bindings/i2c/espressif,esp32-i2c.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_60013000_PATH "/soc/i2c@60013000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_60013000_FULL_NAME "i2c@60013000"
#define DT_N_S_soc_S_i2c_60013000_FULL_NAME_UNQUOTED i2c@60013000
#define DT_N_S_soc_S_i2c_60013000_FULL_NAME_TOKEN i2c_60013000
#define DT_N_S_soc_S_i2c_60013000_FULL_NAME_UPPER_TOKEN I2C_60013000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_60013000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_60013000_CHILD_IDX 20

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_60013000_NODELABEL_NUM 2
#define DT_N_S_soc_S_i2c_60013000_FOREACH_NODELABEL(fn) fn(i2c0) fn(xiao_i2c)
#define DT_N_S_soc_S_i2c_60013000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c0, __VA_ARGS__) fn(xiao_i2c, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_60013000_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_60013000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_60013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_60013000_HASH diC9FjkAugIysmEE2Y8Og0QD8HpYHFYLio2pDvLOy8c

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_60013000_ORD 40
#define DT_N_S_soc_S_i2c_60013000_ORD_STR_SORTABLE 00040

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_60013000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	19, /* /pin-controller/i2c0_default */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_60013000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_60013000_EXISTS 1
#define DT_N_ALIAS_i2c_0                DT_N_S_soc_S_i2c_60013000
#define DT_N_INST_0_espressif_esp32_i2c DT_N_S_soc_S_i2c_60013000
#define DT_N_NODELABEL_i2c0             DT_N_S_soc_S_i2c_60013000
#define DT_N_NODELABEL_xiao_i2c         DT_N_S_soc_S_i2c_60013000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_60013000_REG_NUM 1
#define DT_N_S_soc_S_i2c_60013000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_REG_IDX_0_VAL_ADDRESS 1610690560 /* 0x60013000 */
#define DT_N_S_soc_S_i2c_60013000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2c_60013000_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_60013000, 0)
#define DT_N_S_soc_S_i2c_60013000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, 0)
#define DT_N_S_soc_S_i2c_60013000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_60013000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_60013000_IRQ_NUM 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_irq 42
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60013000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_60013000_COMPAT_MATCHES_espressif_esp32_i2c 1
#define DT_N_S_soc_S_i2c_60013000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_i2c_60013000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_COMPAT_MODEL_IDX_0 "esp32-i2c"
#define DT_N_S_soc_S_i2c_60013000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_NUM 1
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_i2c_60013000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_i2c0_default

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_60013000_P_reg {1610690560 /* 0x60013000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2c_60013000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_reg_IDX_0 1610690560
#define DT_N_S_soc_S_i2c_60013000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2c_60013000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_i2c0_default
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_i2c0_default
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_0, 0)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_names, 0)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_tx_lsb 0
#define DT_N_S_soc_S_i2c_60013000_P_tx_lsb_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_rx_lsb 0
#define DT_N_S_soc_S_i2c_60013000_P_rx_lsb_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_clock_frequency 100000
#define DT_N_S_soc_S_i2c_60013000_P_clock_frequency_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_sq_size 4
#define DT_N_S_soc_S_i2c_60013000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_cq_size 4
#define DT_N_S_soc_S_i2c_60013000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_status "okay"
#define DT_N_S_soc_S_i2c_60013000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_i2c_60013000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_i2c_60013000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_i2c_60013000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_i2c_60013000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_i2c_60013000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, status, 0)
#define DT_N_S_soc_S_i2c_60013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, status, 0)
#define DT_N_S_soc_S_i2c_60013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_status_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_compatible {"espressif,esp32-i2c"}
#define DT_N_S_soc_S_i2c_60013000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_compatible_IDX_0 "espressif,esp32-i2c"
#define DT_N_S_soc_S_i2c_60013000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-i2c
#define DT_N_S_soc_S_i2c_60013000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_i2c
#define DT_N_S_soc_S_i2c_60013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_I2C
#define DT_N_S_soc_S_i2c_60013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, compatible, 0)
#define DT_N_S_soc_S_i2c_60013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, compatible, 0)
#define DT_N_S_soc_S_i2c_60013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupts {42 /* 0x2a */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_0 42
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_i2c_60013000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_VAL_offset 103
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0, offset)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0, offset)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2c_60013000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60013000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60013000_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_60013000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_60013000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_60013000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_60013000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_60013000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2c@60027000
 *
 * Node identifier: DT_N_S_soc_S_i2c_60027000
 *
 * Binding (compatible = espressif,esp32-i2c):
 *   $ZEPHYR_BASE/dts/bindings/i2c/espressif,esp32-i2c.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2c_60027000_PATH "/soc/i2c@60027000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2c_60027000_FULL_NAME "i2c@60027000"
#define DT_N_S_soc_S_i2c_60027000_FULL_NAME_UNQUOTED i2c@60027000
#define DT_N_S_soc_S_i2c_60027000_FULL_NAME_TOKEN i2c_60027000
#define DT_N_S_soc_S_i2c_60027000_FULL_NAME_UPPER_TOKEN I2C_60027000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2c_60027000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2c_60027000_CHILD_IDX 21

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2c_60027000_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2c_60027000_FOREACH_NODELABEL(fn) fn(i2c1)
#define DT_N_S_soc_S_i2c_60027000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2c1, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2c_60027000_CHILD_NUM 0
#define DT_N_S_soc_S_i2c_60027000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2c_60027000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2c_60027000_HASH SXFn1itkpablGfM2xYGAOJbfdg6jx0bi_lt599mkZ8w

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2c_60027000_ORD 41
#define DT_N_S_soc_S_i2c_60027000_ORD_STR_SORTABLE 00041

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2c_60027000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2c_60027000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2c_60027000_EXISTS 1
#define DT_N_INST_1_espressif_esp32_i2c DT_N_S_soc_S_i2c_60027000
#define DT_N_NODELABEL_i2c1             DT_N_S_soc_S_i2c_60027000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2c_60027000_REG_NUM 1
#define DT_N_S_soc_S_i2c_60027000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_REG_IDX_0_VAL_ADDRESS 1610772480 /* 0x60027000 */
#define DT_N_S_soc_S_i2c_60027000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2c_60027000_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2c_60027000, 0)
#define DT_N_S_soc_S_i2c_60027000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, 0)
#define DT_N_S_soc_S_i2c_60027000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60027000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60027000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_RANGES_NUM 0
#define DT_N_S_soc_S_i2c_60027000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2c_60027000_IRQ_NUM 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_irq 43
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60027000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2c_60027000_COMPAT_MATCHES_espressif_esp32_i2c 1
#define DT_N_S_soc_S_i2c_60027000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_i2c_60027000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_COMPAT_MODEL_IDX_0 "esp32-i2c"
#define DT_N_S_soc_S_i2c_60027000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2c_60027000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2c_60027000_P_reg {1610772480 /* 0x60027000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2c_60027000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_reg_IDX_0 1610772480
#define DT_N_S_soc_S_i2c_60027000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2c_60027000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_tx_lsb 0
#define DT_N_S_soc_S_i2c_60027000_P_tx_lsb_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_rx_lsb 0
#define DT_N_S_soc_S_i2c_60027000_P_rx_lsb_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_sq_size 4
#define DT_N_S_soc_S_i2c_60027000_P_sq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_cq_size 4
#define DT_N_S_soc_S_i2c_60027000_P_cq_size_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_status "disabled"
#define DT_N_S_soc_S_i2c_60027000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2c_60027000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2c_60027000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2c_60027000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2c_60027000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2c_60027000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60027000, status, 0)
#define DT_N_S_soc_S_i2c_60027000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, status, 0)
#define DT_N_S_soc_S_i2c_60027000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60027000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60027000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_status_LEN 1
#define DT_N_S_soc_S_i2c_60027000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_compatible {"espressif,esp32-i2c"}
#define DT_N_S_soc_S_i2c_60027000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_compatible_IDX_0 "espressif,esp32-i2c"
#define DT_N_S_soc_S_i2c_60027000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-i2c
#define DT_N_S_soc_S_i2c_60027000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_i2c
#define DT_N_S_soc_S_i2c_60027000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_I2C
#define DT_N_S_soc_S_i2c_60027000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60027000, compatible, 0)
#define DT_N_S_soc_S_i2c_60027000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, compatible, 0)
#define DT_N_S_soc_S_i2c_60027000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60027000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60027000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2c_60027000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_0 43
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_i2c_60027000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60027000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60027000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60027000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_i2c_60027000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_VAL_offset 104
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0, offset)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0, offset)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2c_60027000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_60027000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2c_60027000_P_clocks_LEN 1
#define DT_N_S_soc_S_i2c_60027000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2c_60027000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_wakeup_source 0
#define DT_N_S_soc_S_i2c_60027000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2c_60027000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2c_60027000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/dma@6003f000
 *
 * Node identifier: DT_N_S_soc_S_dma_6003f000
 *
 * Binding (compatible = espressif,esp32-gdma):
 *   $ZEPHYR_BASE/dts/bindings/dma/espressif,esp32-gdma.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_dma_6003f000_PATH "/soc/dma@6003f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_dma_6003f000_FULL_NAME "dma@6003f000"
#define DT_N_S_soc_S_dma_6003f000_FULL_NAME_UNQUOTED dma@6003f000
#define DT_N_S_soc_S_dma_6003f000_FULL_NAME_TOKEN dma_6003f000
#define DT_N_S_soc_S_dma_6003f000_FULL_NAME_UPPER_TOKEN DMA_6003F000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_dma_6003f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_dma_6003f000_CHILD_IDX 44

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_dma_6003f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_dma_6003f000_FOREACH_NODELABEL(fn) fn(dma)
#define DT_N_S_soc_S_dma_6003f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dma, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_dma_6003f000_CHILD_NUM 0
#define DT_N_S_soc_S_dma_6003f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_dma_6003f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_dma_6003f000_HASH ChjKwIh8h_E_Bk6GwR2A6PxkBTP21qk6VLD9eGTpvrc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_dma_6003f000_ORD 42
#define DT_N_S_soc_S_dma_6003f000_ORD_STR_SORTABLE 00042

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_dma_6003f000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_dma_6003f000_SUPPORTS_ORDS \
	43, /* /soc/i2s@6000f000 */ \
	44, /* /soc/i2s@6002d000 */ \
	95, /* /soc/lcd_cam@60041000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_dma_6003f000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_gdma DT_N_S_soc_S_dma_6003f000
#define DT_N_NODELABEL_dma               DT_N_S_soc_S_dma_6003f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_dma_6003f000_REG_NUM 1
#define DT_N_S_soc_S_dma_6003f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_REG_IDX_0_VAL_ADDRESS 1610870784 /* 0x6003f000 */
#define DT_N_S_soc_S_dma_6003f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_dma_6003f000_FOREACH_REG(fn) fn(DT_N_S_soc_S_dma_6003f000, 0)
#define DT_N_S_soc_S_dma_6003f000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, 0)
#define DT_N_S_soc_S_dma_6003f000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_6003f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_6003f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_RANGES_NUM 0
#define DT_N_S_soc_S_dma_6003f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_dma_6003f000_IRQ_NUM 10
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_irq 66
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_irq 71
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_irq 67
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_2_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_irq 72
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_3_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_irq 68
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_4_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_irq 73
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_5_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_irq 69
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_6_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_irq 74
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_7_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_irq 70
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_8_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_irq 75
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_priority 0
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_flags 256
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_IRQ_IDX_9_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_dma_6003f000_COMPAT_MATCHES_espressif_esp32_gdma 1
#define DT_N_S_soc_S_dma_6003f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_dma_6003f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_COMPAT_MODEL_IDX_0 "esp32-gdma"
#define DT_N_S_soc_S_dma_6003f000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_dma_6003f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_dma_6003f000_P_dma_channels 10
#define DT_N_S_soc_S_dma_6003f000_P_dma_channels_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_dma_buf_addr_alignment 4
#define DT_N_S_soc_S_dma_6003f000_P_dma_buf_addr_alignment_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_status "disabled"
#define DT_N_S_soc_S_dma_6003f000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_dma_6003f000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_dma_6003f000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_dma_6003f000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_dma_6003f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_dma_6003f000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_6003f000, status, 0)
#define DT_N_S_soc_S_dma_6003f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, status, 0)
#define DT_N_S_soc_S_dma_6003f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_6003f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_6003f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_status_LEN 1
#define DT_N_S_soc_S_dma_6003f000_P_status_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_compatible {"espressif,esp32-gdma"}
#define DT_N_S_soc_S_dma_6003f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_compatible_IDX_0 "espressif,esp32-gdma"
#define DT_N_S_soc_S_dma_6003f000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-gdma
#define DT_N_S_soc_S_dma_6003f000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_gdma
#define DT_N_S_soc_S_dma_6003f000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_GDMA
#define DT_N_S_soc_S_dma_6003f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_6003f000, compatible, 0)
#define DT_N_S_soc_S_dma_6003f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, compatible, 0)
#define DT_N_S_soc_S_dma_6003f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_6003f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_6003f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_compatible_LEN 1
#define DT_N_S_soc_S_dma_6003f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_reg {1610870784 /* 0x6003f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_dma_6003f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_reg_IDX_0 1610870784
#define DT_N_S_soc_S_dma_6003f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_dma_6003f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts {66 /* 0x42 */, 0 /* 0x0 */, 256 /* 0x100 */, 71 /* 0x47 */, 0 /* 0x0 */, 256 /* 0x100 */, 67 /* 0x43 */, 0 /* 0x0 */, 256 /* 0x100 */, 72 /* 0x48 */, 0 /* 0x0 */, 256 /* 0x100 */, 68 /* 0x44 */, 0 /* 0x0 */, 256 /* 0x100 */, 73 /* 0x49 */, 0 /* 0x0 */, 256 /* 0x100 */, 69 /* 0x45 */, 0 /* 0x0 */, 256 /* 0x100 */, 74 /* 0x4a */, 0 /* 0x0 */, 256 /* 0x100 */, 70 /* 0x46 */, 0 /* 0x0 */, 256 /* 0x100 */, 75 /* 0x4b */, 0 /* 0x0 */, 256 /* 0x100 */}
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_0 66
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_2 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_3 71
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_4 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_5 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_6_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_6 67
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_7_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_7 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_8_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_8 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_9_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_9 72
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_10_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_10 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_11_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_11 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_12_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_12 68
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_13_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_13 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_14_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_14 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_15_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_15 73
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_16_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_16 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_17_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_17 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_18_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_18 69
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_19_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_19 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_20_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_20 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_21_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_21 74
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_22_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_22 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_23_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_23 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_24_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_24 70
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_25_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_25 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_26_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_26 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_27_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_27 75
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_28_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_28 0
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_29_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_IDX_29 256
#define DT_N_S_soc_S_dma_6003f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_6003f000, interrupt_parent, 0)
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, interrupt_parent, 0)
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_6003f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_6003f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_dma_6003f000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_VAL_offset 126
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0, offset)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0, offset)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_dma_6003f000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_6003f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_dma_6003f000_P_clocks_LEN 1
#define DT_N_S_soc_S_dma_6003f000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_dma_6003f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_wakeup_source 0
#define DT_N_S_soc_S_dma_6003f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_dma_6003f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_dma_6003f000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2s@6000f000
 *
 * Node identifier: DT_N_S_soc_S_i2s_6000f000
 *
 * Binding (compatible = espressif,esp32-i2s):
 *   $ZEPHYR_BASE/dts/bindings/i2s/espressif,esp32-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2s_6000f000_PATH "/soc/i2s@6000f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2s_6000f000_FULL_NAME "i2s@6000f000"
#define DT_N_S_soc_S_i2s_6000f000_FULL_NAME_UNQUOTED i2s@6000f000
#define DT_N_S_soc_S_i2s_6000f000_FULL_NAME_TOKEN i2s_6000f000
#define DT_N_S_soc_S_i2s_6000f000_FULL_NAME_UPPER_TOKEN I2S_6000F000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2s_6000f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2s_6000f000_CHILD_IDX 22

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2s_6000f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_NODELABEL(fn) fn(i2s0)
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2s_6000f000_CHILD_NUM 0
#define DT_N_S_soc_S_i2s_6000f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2s_6000f000_HASH FjABTBTGl9eAwVAd5LyPSHuYHqhjqDz_ivspLhd8GRg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2s_6000f000_ORD 43
#define DT_N_S_soc_S_i2s_6000f000_ORD_STR_SORTABLE 00043

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2s_6000f000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */ \
	42, /* /soc/dma@6003f000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2s_6000f000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2s_6000f000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_i2s DT_N_S_soc_S_i2s_6000f000
#define DT_N_NODELABEL_i2s0             DT_N_S_soc_S_i2s_6000f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2s_6000f000_REG_NUM 1
#define DT_N_S_soc_S_i2s_6000f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_REG_IDX_0_VAL_ADDRESS 1610674176 /* 0x6000f000 */
#define DT_N_S_soc_S_i2s_6000f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2s_6000f000, 0)
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, 0)
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_RANGES_NUM 0
#define DT_N_S_soc_S_i2s_6000f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2s_6000f000_IRQ_NUM 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_irq 25
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6000f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2s_6000f000_COMPAT_MATCHES_espressif_esp32_i2s 1
#define DT_N_S_soc_S_i2s_6000f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_i2s_6000f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_COMPAT_MODEL_IDX_0 "esp32-i2s"
#define DT_N_S_soc_S_i2s_6000f000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2s_6000f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2s_6000f000_P_reg {1610674176 /* 0x6000f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2s_6000f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_reg_IDX_0 1610674176
#define DT_N_S_soc_S_i2s_6000f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2s_6000f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_VAL_offset 105
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0, offset)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0, offset)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_LEN 1
#define DT_N_S_soc_S_i2s_6000f000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts {25 /* 0x19 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_0 25
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_i2s_6000f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_i2s_6000f000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_unit 0
#define DT_N_S_soc_S_i2s_6000f000_P_unit_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_status "disabled"
#define DT_N_S_soc_S_i2s_6000f000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2s_6000f000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2s_6000f000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_6000f000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2s_6000f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2s_6000f000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, status, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, status, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_status_LEN 1
#define DT_N_S_soc_S_i2s_6000f000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_compatible {"espressif,esp32-i2s"}
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_IDX_0 "espressif,esp32-i2s"
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-i2s
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_i2s
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_I2S
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, compatible, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, compatible, 0)
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2s_6000f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_VAL_channel 2
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_NAME "rx"
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_IDX 0
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6000f000, dmas, rx, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dmas, rx, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_VAL_channel DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_0_VAL_channel
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_VAL_channel 3
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_NAME "tx"
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_IDX 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6000f000, dmas, tx, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dmas, tx, channel)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_VAL_channel DT_N_S_soc_S_i2s_6000f000_P_dmas_IDX_1_VAL_channel
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0) \
	fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, dmas, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6000f000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_LEN 2
#define DT_N_S_soc_S_i2s_6000f000_P_dmas_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names {"rx", "tx"}
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_0 "rx"
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_0_STRING_UNQUOTED rx
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_0_STRING_TOKEN rx
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_0_STRING_UPPER_TOKEN RX
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_1 "tx"
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_1_STRING_UNQUOTED tx
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_1_STRING_TOKEN tx
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_IDX_1_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 0) \
	fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 1)
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 1)
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6000f000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_LEN 2
#define DT_N_S_soc_S_i2s_6000f000_P_dma_names_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2s_6000f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_wakeup_source 0
#define DT_N_S_soc_S_i2s_6000f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2s_6000f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2s_6000f000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/i2s@6002d000
 *
 * Node identifier: DT_N_S_soc_S_i2s_6002d000
 *
 * Binding (compatible = espressif,esp32-i2s):
 *   $ZEPHYR_BASE/dts/bindings/i2s/espressif,esp32-i2s.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_i2s_6002d000_PATH "/soc/i2s@6002d000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_i2s_6002d000_FULL_NAME "i2s@6002d000"
#define DT_N_S_soc_S_i2s_6002d000_FULL_NAME_UNQUOTED i2s@6002d000
#define DT_N_S_soc_S_i2s_6002d000_FULL_NAME_TOKEN i2s_6002d000
#define DT_N_S_soc_S_i2s_6002d000_FULL_NAME_UPPER_TOKEN I2S_6002D000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_i2s_6002d000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_i2s_6002d000_CHILD_IDX 23

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_i2s_6002d000_NODELABEL_NUM 1
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_NODELABEL(fn) fn(i2s1)
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_NODELABEL_VARGS(fn, ...) fn(i2s1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_i2s_6002d000_CHILD_NUM 0
#define DT_N_S_soc_S_i2s_6002d000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_i2s_6002d000_HASH CUHU_JCAgzfutPFLKs94Sa_Ao6CXCFxQLlCNi0J1Jl0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_i2s_6002d000_ORD 44
#define DT_N_S_soc_S_i2s_6002d000_ORD_STR_SORTABLE 00044

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_i2s_6002d000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */ \
	42, /* /soc/dma@6003f000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_i2s_6002d000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_i2s_6002d000_EXISTS 1
#define DT_N_INST_1_espressif_esp32_i2s DT_N_S_soc_S_i2s_6002d000
#define DT_N_NODELABEL_i2s1             DT_N_S_soc_S_i2s_6002d000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_i2s_6002d000_REG_NUM 1
#define DT_N_S_soc_S_i2s_6002d000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_REG_IDX_0_VAL_ADDRESS 1610797056 /* 0x6002d000 */
#define DT_N_S_soc_S_i2s_6002d000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_REG(fn) fn(DT_N_S_soc_S_i2s_6002d000, 0)
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, 0)
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_RANGES_NUM 0
#define DT_N_S_soc_S_i2s_6002d000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_i2s_6002d000_IRQ_NUM 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_irq 26
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6002d000_IRQ_LEVEL 1
#define DT_N_S_soc_S_i2s_6002d000_COMPAT_MATCHES_espressif_esp32_i2s 1
#define DT_N_S_soc_S_i2s_6002d000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_i2s_6002d000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_COMPAT_MODEL_IDX_0 "esp32-i2s"
#define DT_N_S_soc_S_i2s_6002d000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_i2s_6002d000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_i2s_6002d000_P_reg {1610797056 /* 0x6002d000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_i2s_6002d000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_reg_IDX_0 1610797056
#define DT_N_S_soc_S_i2s_6002d000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_i2s_6002d000_P_reg_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_VAL_offset 106
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0, offset)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0, offset)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_LEN 1
#define DT_N_S_soc_S_i2s_6002d000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts {26 /* 0x1a */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_0 26
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_i2s_6002d000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, interrupt_parent, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_i2s_6002d000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_unit 1
#define DT_N_S_soc_S_i2s_6002d000_P_unit_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_status "disabled"
#define DT_N_S_soc_S_i2s_6002d000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_i2s_6002d000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_i2s_6002d000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_i2s_6002d000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_i2s_6002d000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_i2s_6002d000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, status, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, status, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_status_LEN 1
#define DT_N_S_soc_S_i2s_6002d000_P_status_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_compatible {"espressif,esp32-i2s"}
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_IDX_0 "espressif,esp32-i2s"
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-i2s
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_i2s
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_I2S
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, compatible, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, compatible, 0)
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_LEN 1
#define DT_N_S_soc_S_i2s_6002d000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_VAL_channel 4
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_NAME "rx"
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_IDX 0
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6002d000, dmas, rx, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dmas, rx, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_VAL_channel DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_0_VAL_channel
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_VAL_channel 5
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_NAME "tx"
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_IDX 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_i2s_6002d000, dmas, tx, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dmas, tx, channel)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_NUM_CELLS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_VAL_channel DT_N_S_soc_S_i2s_6002d000_P_dmas_IDX_1_VAL_channel
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0) \
	fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, dmas, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6002d000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_LEN 2
#define DT_N_S_soc_S_i2s_6002d000_P_dmas_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names {"rx", "tx"}
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_0 "rx"
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_0_STRING_UNQUOTED rx
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_0_STRING_TOKEN rx
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_0_STRING_UPPER_TOKEN RX
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_1 "tx"
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_1_STRING_UNQUOTED tx
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_1_STRING_TOKEN tx
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_IDX_1_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 0) \
	fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 1)
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 1)
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_i2s_6002d000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_LEN 2
#define DT_N_S_soc_S_i2s_6002d000_P_dma_names_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_i2s_6002d000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_wakeup_source 0
#define DT_N_S_soc_S_i2s_6002d000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_i2s_6002d000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_i2s_6002d000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@3fce5000
 *
 * Node identifier: DT_N_S_soc_S_memory_3fce5000
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3fce5000_PATH "/soc/memory@3fce5000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3fce5000_FULL_NAME "memory@3fce5000"
#define DT_N_S_soc_S_memory_3fce5000_FULL_NAME_UNQUOTED memory@3fce5000
#define DT_N_S_soc_S_memory_3fce5000_FULL_NAME_TOKEN memory_3fce5000
#define DT_N_S_soc_S_memory_3fce5000_FULL_NAME_UPPER_TOKEN MEMORY_3FCE5000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_3fce5000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3fce5000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3fce5000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_NODELABEL(fn) fn(ipmmem0)
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ipmmem0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3fce5000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_3fce5000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_3fce5000_HASH ya9e7l8G8HZIHSt4qOsMkzjAb8gpBz1H5_xZF9aaKR8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3fce5000_ORD 45
#define DT_N_S_soc_S_memory_3fce5000_ORD_STR_SORTABLE 00045

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3fce5000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3fce5000_SUPPORTS_ORDS \
	46, /* /soc/ipm@3fce9400 */ \
	48, /* /soc/mbox@3fce9408 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3fce5000_EXISTS 1
#define DT_N_INST_3_mmio_sram  DT_N_S_soc_S_memory_3fce5000
#define DT_N_NODELABEL_ipmmem0 DT_N_S_soc_S_memory_3fce5000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3fce5000_REG_NUM 1
#define DT_N_S_soc_S_memory_3fce5000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_REG_IDX_0_VAL_ADDRESS 1070485504 /* 0x3fce5000 */
#define DT_N_S_soc_S_memory_3fce5000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_3fce5000, 0)
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fce5000, 0)
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fce5000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fce5000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3fce5000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3fce5000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3fce5000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3fce5000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_3fce5000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3fce5000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3fce5000_P_reg {1070485504 /* 0x3fce5000 */, 1024 /* 0x400 */}
#define DT_N_S_soc_S_memory_3fce5000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_reg_IDX_0 1070485504
#define DT_N_S_soc_S_memory_3fce5000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_reg_IDX_1 1024
#define DT_N_S_soc_S_memory_3fce5000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fce5000, compatible, 0)
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fce5000, compatible, 0)
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fce5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fce5000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_3fce5000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3fce5000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3fce5000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3fce5000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/ipm@3fce9400
 *
 * Node identifier: DT_N_S_soc_S_ipm_3fce9400
 *
 * Binding (compatible = espressif,esp32-ipm):
 *   $ZEPHYR_BASE/dts/bindings/ipm/espressif,esp32-ipm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ipm_3fce9400_PATH "/soc/ipm@3fce9400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ipm_3fce9400_FULL_NAME "ipm@3fce9400"
#define DT_N_S_soc_S_ipm_3fce9400_FULL_NAME_UNQUOTED ipm@3fce9400
#define DT_N_S_soc_S_ipm_3fce9400_FULL_NAME_TOKEN ipm_3fce9400
#define DT_N_S_soc_S_ipm_3fce9400_FULL_NAME_UPPER_TOKEN IPM_3FCE9400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ipm_3fce9400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ipm_3fce9400_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ipm_3fce9400_NODELABEL_NUM 1
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_NODELABEL(fn) fn(ipm0)
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_NODELABEL_VARGS(fn, ...) fn(ipm0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ipm_3fce9400_CHILD_NUM 0
#define DT_N_S_soc_S_ipm_3fce9400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_ipm_3fce9400_HASH qFVyhyJjCS_P9l2H5RUk6F_EjPj1jBYx7tKjRARaO5I

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ipm_3fce9400_ORD 46
#define DT_N_S_soc_S_ipm_3fce9400_ORD_STR_SORTABLE 00046

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ipm_3fce9400_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	45, /* /soc/memory@3fce5000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ipm_3fce9400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ipm_3fce9400_EXISTS 1
#define DT_N_INST_0_espressif_esp32_ipm DT_N_S_soc_S_ipm_3fce9400
#define DT_N_NODELABEL_ipm0             DT_N_S_soc_S_ipm_3fce9400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ipm_3fce9400_REG_NUM 1
#define DT_N_S_soc_S_ipm_3fce9400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_REG_IDX_0_VAL_ADDRESS 1070502912 /* 0x3fce9400 */
#define DT_N_S_soc_S_ipm_3fce9400_REG_IDX_0_VAL_SIZE 8 /* 0x8 */
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_REG(fn) fn(DT_N_S_soc_S_ipm_3fce9400, 0)
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_ipm_3fce9400, 0)
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_ipm_3fce9400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ipm_3fce9400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_RANGES_NUM 0
#define DT_N_S_soc_S_ipm_3fce9400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_NUM 2
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_irq 79
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_irq 80
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_flags 0
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_ipm_3fce9400_IRQ_LEVEL 1
#define DT_N_S_soc_S_ipm_3fce9400_COMPAT_MATCHES_espressif_esp32_ipm 1
#define DT_N_S_soc_S_ipm_3fce9400_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_ipm_3fce9400_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_COMPAT_MODEL_IDX_0 "esp32-ipm"
#define DT_N_S_soc_S_ipm_3fce9400_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ipm_3fce9400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ipm_3fce9400_P_reg {1070502912 /* 0x3fce9400 */, 8 /* 0x8 */}
#define DT_N_S_soc_S_ipm_3fce9400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_reg_IDX_0 1070502912
#define DT_N_S_soc_S_ipm_3fce9400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_reg_IDX_1 8
#define DT_N_S_soc_S_ipm_3fce9400_P_reg_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_IDX_0 DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_IDX_0_PH DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ipm_3fce9400, shared_memory, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ipm_3fce9400, shared_memory, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ipm_3fce9400, shared_memory, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ipm_3fce9400, shared_memory, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_LEN 1
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_size 1024
#define DT_N_S_soc_S_ipm_3fce9400_P_shared_memory_size_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts {79 /* 0x4f */, 0 /* 0x0 */, 0 /* 0x0 */, 80 /* 0x50 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_0 79
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_3 80
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_4 0
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status "disabled"
#define DT_N_S_soc_S_ipm_3fce9400_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_ipm_3fce9400_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_ipm_3fce9400_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_ipm_3fce9400_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_ipm_3fce9400_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ipm_3fce9400, status, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ipm_3fce9400, status, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ipm_3fce9400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ipm_3fce9400, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_status_LEN 1
#define DT_N_S_soc_S_ipm_3fce9400_P_status_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible {"espressif,esp32-ipm"}
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_IDX_0 "espressif,esp32-ipm"
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-ipm
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_ipm
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_IPM
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ipm_3fce9400, compatible, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ipm_3fce9400, compatible, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ipm_3fce9400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ipm_3fce9400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_LEN 1
#define DT_N_S_soc_S_ipm_3fce9400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ipm_3fce9400, interrupt_parent, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ipm_3fce9400, interrupt_parent, 0)
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ipm_3fce9400, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ipm_3fce9400, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_ipm_3fce9400_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ipm_3fce9400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_wakeup_source 0
#define DT_N_S_soc_S_ipm_3fce9400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ipm_3fce9400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ipm_3fce9400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/ledc@60019000
 *
 * Node identifier: DT_N_S_soc_S_ledc_60019000
 *
 * Binding (compatible = espressif,esp32-ledc):
 *   $ZEPHYR_BASE/dts/bindings/pwm/espressif,esp32-ledc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_ledc_60019000_PATH "/soc/ledc@60019000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_ledc_60019000_FULL_NAME "ledc@60019000"
#define DT_N_S_soc_S_ledc_60019000_FULL_NAME_UNQUOTED ledc@60019000
#define DT_N_S_soc_S_ledc_60019000_FULL_NAME_TOKEN ledc_60019000
#define DT_N_S_soc_S_ledc_60019000_FULL_NAME_UPPER_TOKEN LEDC_60019000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_ledc_60019000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_ledc_60019000_CHILD_IDX 40

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_ledc_60019000_NODELABEL_NUM 1
#define DT_N_S_soc_S_ledc_60019000_FOREACH_NODELABEL(fn) fn(ledc0)
#define DT_N_S_soc_S_ledc_60019000_FOREACH_NODELABEL_VARGS(fn, ...) fn(ledc0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_ledc_60019000_CHILD_NUM 0
#define DT_N_S_soc_S_ledc_60019000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_ledc_60019000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_ledc_60019000_HASH ivU7PYnXftTq8IeHZYedNtxFhGTursL0wzBinUM6lpI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_ledc_60019000_ORD 47
#define DT_N_S_soc_S_ledc_60019000_ORD_STR_SORTABLE 00047

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_ledc_60019000_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_ledc_60019000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_ledc_60019000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_ledc DT_N_S_soc_S_ledc_60019000
#define DT_N_NODELABEL_ledc0             DT_N_S_soc_S_ledc_60019000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_ledc_60019000_REG_NUM 1
#define DT_N_S_soc_S_ledc_60019000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_REG_IDX_0_VAL_ADDRESS 1610715136 /* 0x60019000 */
#define DT_N_S_soc_S_ledc_60019000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_ledc_60019000_FOREACH_REG(fn) fn(DT_N_S_soc_S_ledc_60019000, 0)
#define DT_N_S_soc_S_ledc_60019000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_ledc_60019000, 0)
#define DT_N_S_soc_S_ledc_60019000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_ledc_60019000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ledc_60019000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_RANGES_NUM 0
#define DT_N_S_soc_S_ledc_60019000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_ledc_60019000_IRQ_NUM 0
#define DT_N_S_soc_S_ledc_60019000_IRQ_LEVEL 0
#define DT_N_S_soc_S_ledc_60019000_COMPAT_MATCHES_espressif_esp32_ledc 1
#define DT_N_S_soc_S_ledc_60019000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_ledc_60019000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_COMPAT_MODEL_IDX_0 "esp32-ledc"
#define DT_N_S_soc_S_ledc_60019000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_ledc_60019000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_ledc_60019000_P_status "disabled"
#define DT_N_S_soc_S_ledc_60019000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_ledc_60019000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_ledc_60019000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_ledc_60019000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_ledc_60019000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_ledc_60019000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ledc_60019000, status, 0)
#define DT_N_S_soc_S_ledc_60019000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ledc_60019000, status, 0)
#define DT_N_S_soc_S_ledc_60019000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ledc_60019000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ledc_60019000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_status_LEN 1
#define DT_N_S_soc_S_ledc_60019000_P_status_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_compatible {"espressif,esp32-ledc"}
#define DT_N_S_soc_S_ledc_60019000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_compatible_IDX_0 "espressif,esp32-ledc"
#define DT_N_S_soc_S_ledc_60019000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-ledc
#define DT_N_S_soc_S_ledc_60019000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_ledc
#define DT_N_S_soc_S_ledc_60019000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_LEDC
#define DT_N_S_soc_S_ledc_60019000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ledc_60019000, compatible, 0)
#define DT_N_S_soc_S_ledc_60019000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ledc_60019000, compatible, 0)
#define DT_N_S_soc_S_ledc_60019000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ledc_60019000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ledc_60019000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_compatible_LEN 1
#define DT_N_S_soc_S_ledc_60019000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_reg {1610715136 /* 0x60019000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_ledc_60019000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_reg_IDX_0 1610715136
#define DT_N_S_soc_S_ledc_60019000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_ledc_60019000_P_reg_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_VAL_offset 100
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0, offset)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0, offset)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_ledc_60019000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ledc_60019000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_ledc_60019000_P_clocks_LEN 1
#define DT_N_S_soc_S_ledc_60019000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_ledc_60019000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_wakeup_source 0
#define DT_N_S_soc_S_ledc_60019000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_ledc_60019000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_ledc_60019000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/mbox@3fce9408
 *
 * Node identifier: DT_N_S_soc_S_mbox_3fce9408
 *
 * Binding (compatible = espressif,mbox-esp32):
 *   $ZEPHYR_BASE/dts/bindings/mbox/espressif,mbox-esp32.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_mbox_3fce9408_PATH "/soc/mbox@3fce9408"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_mbox_3fce9408_FULL_NAME "mbox@3fce9408"
#define DT_N_S_soc_S_mbox_3fce9408_FULL_NAME_UNQUOTED mbox@3fce9408
#define DT_N_S_soc_S_mbox_3fce9408_FULL_NAME_TOKEN mbox_3fce9408
#define DT_N_S_soc_S_mbox_3fce9408_FULL_NAME_UPPER_TOKEN MBOX_3FCE9408

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_mbox_3fce9408_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_mbox_3fce9408_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_mbox_3fce9408_NODELABEL_NUM 1
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_NODELABEL(fn) fn(mbox0)
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_NODELABEL_VARGS(fn, ...) fn(mbox0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_mbox_3fce9408_CHILD_NUM 0
#define DT_N_S_soc_S_mbox_3fce9408_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_mbox_3fce9408_HASH CosCUcT4QYF3AwJ9hsmzi36XhtEon24YH1I4oPBTXP0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_mbox_3fce9408_ORD 48
#define DT_N_S_soc_S_mbox_3fce9408_ORD_STR_SORTABLE 00048

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_mbox_3fce9408_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	45, /* /soc/memory@3fce5000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_mbox_3fce9408_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_mbox_3fce9408_EXISTS 1
#define DT_N_INST_0_espressif_mbox_esp32 DT_N_S_soc_S_mbox_3fce9408
#define DT_N_NODELABEL_mbox0             DT_N_S_soc_S_mbox_3fce9408

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_mbox_3fce9408_REG_NUM 1
#define DT_N_S_soc_S_mbox_3fce9408_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_REG_IDX_0_VAL_ADDRESS 1070502920 /* 0x3fce9408 */
#define DT_N_S_soc_S_mbox_3fce9408_REG_IDX_0_VAL_SIZE 8 /* 0x8 */
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_REG(fn) fn(DT_N_S_soc_S_mbox_3fce9408, 0)
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_mbox_3fce9408, 0)
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_mbox_3fce9408, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mbox_3fce9408, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_RANGES_NUM 0
#define DT_N_S_soc_S_mbox_3fce9408_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_NUM 2
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_irq 79
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_irq 80
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_priority 0
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_flags 0
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_IDX_1_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mbox_3fce9408_IRQ_LEVEL 1
#define DT_N_S_soc_S_mbox_3fce9408_COMPAT_MATCHES_espressif_mbox_esp32 1
#define DT_N_S_soc_S_mbox_3fce9408_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_mbox_3fce9408_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_COMPAT_MODEL_IDX_0 "mbox-esp32"
#define DT_N_S_soc_S_mbox_3fce9408_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_mbox_3fce9408_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_mbox_3fce9408_P_reg {1070502920 /* 0x3fce9408 */, 8 /* 0x8 */}
#define DT_N_S_soc_S_mbox_3fce9408_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_reg_IDX_0 1070502920
#define DT_N_S_soc_S_mbox_3fce9408_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_reg_IDX_1 8
#define DT_N_S_soc_S_mbox_3fce9408_P_reg_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_IDX_0 DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_IDX_0_PH DT_N_S_soc_S_memory_3fce5000
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mbox_3fce9408, shared_memory, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mbox_3fce9408, shared_memory, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mbox_3fce9408, shared_memory, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mbox_3fce9408, shared_memory, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_LEN 1
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_size 1024
#define DT_N_S_soc_S_mbox_3fce9408_P_shared_memory_size_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts {79 /* 0x4f */, 0 /* 0x0 */, 0 /* 0x0 */, 80 /* 0x50 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_0 79
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_3_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_3 80
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_4_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_4 0
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_5_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_IDX_5 0
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status "disabled"
#define DT_N_S_soc_S_mbox_3fce9408_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_mbox_3fce9408_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_mbox_3fce9408_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_mbox_3fce9408_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_mbox_3fce9408_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mbox_3fce9408, status, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mbox_3fce9408, status, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mbox_3fce9408, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mbox_3fce9408, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_status_LEN 1
#define DT_N_S_soc_S_mbox_3fce9408_P_status_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible {"espressif,mbox-esp32"}
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_IDX_0 "espressif,mbox-esp32"
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_IDX_0_STRING_UNQUOTED espressif,mbox-esp32
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_IDX_0_STRING_TOKEN espressif_mbox_esp32
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_MBOX_ESP32
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mbox_3fce9408, compatible, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mbox_3fce9408, compatible, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mbox_3fce9408, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mbox_3fce9408, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_LEN 1
#define DT_N_S_soc_S_mbox_3fce9408_P_compatible_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mbox_3fce9408, interrupt_parent, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mbox_3fce9408, interrupt_parent, 0)
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mbox_3fce9408, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mbox_3fce9408, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_mbox_3fce9408_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_mbox_3fce9408_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_wakeup_source 0
#define DT_N_S_soc_S_mbox_3fce9408_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_mbox_3fce9408_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_mbox_3fce9408_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/mcpwm@6001e000
 *
 * Node identifier: DT_N_S_soc_S_mcpwm_6001e000
 *
 * Binding (compatible = espressif,esp32-mcpwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/espressif,esp32-mcpwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_mcpwm_6001e000_PATH "/soc/mcpwm@6001e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_mcpwm_6001e000_FULL_NAME "mcpwm@6001e000"
#define DT_N_S_soc_S_mcpwm_6001e000_FULL_NAME_UNQUOTED mcpwm@6001e000
#define DT_N_S_soc_S_mcpwm_6001e000_FULL_NAME_TOKEN mcpwm_6001e000
#define DT_N_S_soc_S_mcpwm_6001e000_FULL_NAME_UPPER_TOKEN MCPWM_6001E000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_mcpwm_6001e000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_mcpwm_6001e000_CHILD_IDX 41

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_mcpwm_6001e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_NODELABEL(fn) fn(mcpwm0)
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mcpwm0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_mcpwm_6001e000_CHILD_NUM 0
#define DT_N_S_soc_S_mcpwm_6001e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_mcpwm_6001e000_HASH d2zHyqMaNADc7KUR4_WygPeNIvvIsUg3nTPCIEFKSWg

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_mcpwm_6001e000_ORD 49
#define DT_N_S_soc_S_mcpwm_6001e000_ORD_STR_SORTABLE 00049

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_mcpwm_6001e000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_mcpwm_6001e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_mcpwm_6001e000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_mcpwm DT_N_S_soc_S_mcpwm_6001e000
#define DT_N_NODELABEL_mcpwm0             DT_N_S_soc_S_mcpwm_6001e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_mcpwm_6001e000_REG_NUM 1
#define DT_N_S_soc_S_mcpwm_6001e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_REG_IDX_0_VAL_ADDRESS 1610735616 /* 0x6001e000 */
#define DT_N_S_soc_S_mcpwm_6001e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_REG(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_RANGES_NUM 0
#define DT_N_S_soc_S_mcpwm_6001e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_NUM 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_irq 31
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6001e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_mcpwm_6001e000_COMPAT_MATCHES_espressif_esp32_mcpwm 1
#define DT_N_S_soc_S_mcpwm_6001e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_mcpwm_6001e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_COMPAT_MODEL_IDX_0 "esp32-mcpwm"
#define DT_N_S_soc_S_mcpwm_6001e000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_mcpwm_6001e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_mcpwm_6001e000_P_status "disabled"
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, status, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, status, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_LEN 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_status_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible {"espressif,esp32-mcpwm"}
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_IDX_0 "espressif,esp32-mcpwm"
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-mcpwm
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_mcpwm
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_MCPWM
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, compatible, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, compatible, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_LEN 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg {1610735616 /* 0x6001e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg_IDX_0 1610735616
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_mcpwm_6001e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts {31 /* 0x1f */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_0 31
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, interrupt_parent, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, interrupt_parent, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_VAL_offset 107
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0, offset)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0, offset)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6001e000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_LEN 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_mcpwm_6001e000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_wakeup_source 0
#define DT_N_S_soc_S_mcpwm_6001e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6001e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_mcpwm_6001e000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/mcpwm@6002c000
 *
 * Node identifier: DT_N_S_soc_S_mcpwm_6002c000
 *
 * Binding (compatible = espressif,esp32-mcpwm):
 *   $ZEPHYR_BASE/dts/bindings/pwm/espressif,esp32-mcpwm.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_mcpwm_6002c000_PATH "/soc/mcpwm@6002c000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_mcpwm_6002c000_FULL_NAME "mcpwm@6002c000"
#define DT_N_S_soc_S_mcpwm_6002c000_FULL_NAME_UNQUOTED mcpwm@6002c000
#define DT_N_S_soc_S_mcpwm_6002c000_FULL_NAME_TOKEN mcpwm_6002c000
#define DT_N_S_soc_S_mcpwm_6002c000_FULL_NAME_UPPER_TOKEN MCPWM_6002C000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_mcpwm_6002c000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_mcpwm_6002c000_CHILD_IDX 42

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_mcpwm_6002c000_NODELABEL_NUM 1
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_NODELABEL(fn) fn(mcpwm1)
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_NODELABEL_VARGS(fn, ...) fn(mcpwm1, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_mcpwm_6002c000_CHILD_NUM 0
#define DT_N_S_soc_S_mcpwm_6002c000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_mcpwm_6002c000_HASH PUT9fuKEmWfw0Ikkb4eK52xX7q1kAZDHic3xFwhvGrw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_mcpwm_6002c000_ORD 50
#define DT_N_S_soc_S_mcpwm_6002c000_ORD_STR_SORTABLE 00050

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_mcpwm_6002c000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_mcpwm_6002c000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_mcpwm_6002c000_EXISTS 1
#define DT_N_INST_1_espressif_esp32_mcpwm DT_N_S_soc_S_mcpwm_6002c000
#define DT_N_NODELABEL_mcpwm1             DT_N_S_soc_S_mcpwm_6002c000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_mcpwm_6002c000_REG_NUM 1
#define DT_N_S_soc_S_mcpwm_6002c000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_REG_IDX_0_VAL_ADDRESS 1610792960 /* 0x6002c000 */
#define DT_N_S_soc_S_mcpwm_6002c000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_REG(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_RANGES_NUM 0
#define DT_N_S_soc_S_mcpwm_6002c000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_NUM 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_irq 32
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6002c000_IRQ_LEVEL 1
#define DT_N_S_soc_S_mcpwm_6002c000_COMPAT_MATCHES_espressif_esp32_mcpwm 1
#define DT_N_S_soc_S_mcpwm_6002c000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_mcpwm_6002c000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_COMPAT_MODEL_IDX_0 "esp32-mcpwm"
#define DT_N_S_soc_S_mcpwm_6002c000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_mcpwm_6002c000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_mcpwm_6002c000_P_status "disabled"
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, status, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, status, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_LEN 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_status_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible {"espressif,esp32-mcpwm"}
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_IDX_0 "espressif,esp32-mcpwm"
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-mcpwm
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_mcpwm
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_MCPWM
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, compatible, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, compatible, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_LEN 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg {1610792960 /* 0x6002c000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg_IDX_0 1610792960
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_mcpwm_6002c000_P_reg_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts {32 /* 0x20 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_0 32
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, interrupt_parent, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, interrupt_parent, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_VAL_offset 108
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0, offset)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0, offset)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mcpwm_6002c000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_LEN 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_mcpwm_6002c000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_wakeup_source 0
#define DT_N_S_soc_S_mcpwm_6002c000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_mcpwm_6002c000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_mcpwm_6002c000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@3fc88000
 *
 * Node identifier: DT_N_S_soc_S_memory_3fc88000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3fc88000_PATH "/soc/memory@3fc88000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3fc88000_FULL_NAME "memory@3fc88000"
#define DT_N_S_soc_S_memory_3fc88000_FULL_NAME_UNQUOTED memory@3fc88000
#define DT_N_S_soc_S_memory_3fc88000_FULL_NAME_TOKEN memory_3fc88000
#define DT_N_S_soc_S_memory_3fc88000_FULL_NAME_UPPER_TOKEN MEMORY_3FC88000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_3fc88000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3fc88000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3fc88000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_NODELABEL(fn) fn(sram1)
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3fc88000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_3fc88000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_3fc88000_HASH dREbOCBoDHQVTmeX36l4_QWq7LHenwdZ_LEoY85fiiI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3fc88000_ORD 51
#define DT_N_S_soc_S_memory_3fc88000_ORD_STR_SORTABLE 00051

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3fc88000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3fc88000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3fc88000_EXISTS 1
#define DT_N_INST_3_zephyr_memory_region DT_N_S_soc_S_memory_3fc88000
#define DT_N_INST_1_mmio_sram            DT_N_S_soc_S_memory_3fc88000
#define DT_N_NODELABEL_sram1             DT_N_S_soc_S_memory_3fc88000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3fc88000_REG_NUM 1
#define DT_N_S_soc_S_memory_3fc88000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_REG_IDX_0_VAL_ADDRESS 1070104576 /* 0x3fc88000 */
#define DT_N_S_soc_S_memory_3fc88000_REG_IDX_0_VAL_SIZE 425984 /* 0x68000 */
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_3fc88000, 0)
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fc88000, 0)
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fc88000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fc88000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3fc88000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3fc88000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3fc88000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_3fc88000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_3fc88000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3fc88000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region "SRAM1"
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_STRING_UNQUOTED SRAM1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_STRING_TOKEN SRAM1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_IDX_0 "SRAM1"
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fc88000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fc88000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fc88000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fc88000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fc88000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_3fc88000, compatible, 1)
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fc88000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_3fc88000, compatible, 1)
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fc88000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_3fc88000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fc88000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_3fc88000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_3fc88000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_reg {1070104576 /* 0x3fc88000 */, 425984 /* 0x68000 */}
#define DT_N_S_soc_S_memory_3fc88000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_reg_IDX_0 1070104576
#define DT_N_S_soc_S_memory_3fc88000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_reg_IDX_1 425984
#define DT_N_S_soc_S_memory_3fc88000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3fc88000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3fc88000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@3fce5400
 *
 * Node identifier: DT_N_S_soc_S_memory_3fce5400
 *
 * Binding (compatible = mmio-sram):
 *   $ZEPHYR_BASE/dts/bindings/sram/mmio-sram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3fce5400_PATH "/soc/memory@3fce5400"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3fce5400_FULL_NAME "memory@3fce5400"
#define DT_N_S_soc_S_memory_3fce5400_FULL_NAME_UNQUOTED memory@3fce5400
#define DT_N_S_soc_S_memory_3fce5400_FULL_NAME_TOKEN memory_3fce5400
#define DT_N_S_soc_S_memory_3fce5400_FULL_NAME_UPPER_TOKEN MEMORY_3FCE5400

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_3fce5400_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3fce5400_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3fce5400_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_NODELABEL(fn) fn(shm0)
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_NODELABEL_VARGS(fn, ...) fn(shm0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3fce5400_CHILD_NUM 0
#define DT_N_S_soc_S_memory_3fce5400_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_3fce5400_HASH HyL82Z6ujffmB6CBSFiHfwfgvsYwqIL4lYGisoVn_Gc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3fce5400_ORD 52
#define DT_N_S_soc_S_memory_3fce5400_ORD_STR_SORTABLE 00052

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3fce5400_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3fce5400_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3fce5400_EXISTS 1
#define DT_N_INST_4_mmio_sram DT_N_S_soc_S_memory_3fce5400
#define DT_N_NODELABEL_shm0   DT_N_S_soc_S_memory_3fce5400

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3fce5400_REG_NUM 1
#define DT_N_S_soc_S_memory_3fce5400_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_REG_IDX_0_VAL_ADDRESS 1070486528 /* 0x3fce5400 */
#define DT_N_S_soc_S_memory_3fce5400_REG_IDX_0_VAL_SIZE 16384 /* 0x4000 */
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_3fce5400, 0)
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fce5400, 0)
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fce5400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fce5400, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5400_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3fce5400_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3fce5400_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3fce5400_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3fce5400_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_3fce5400_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3fce5400_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3fce5400_P_reg {1070486528 /* 0x3fce5400 */, 16384 /* 0x4000 */}
#define DT_N_S_soc_S_memory_3fce5400_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_reg_IDX_0 1070486528
#define DT_N_S_soc_S_memory_3fce5400_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_reg_IDX_1 16384
#define DT_N_S_soc_S_memory_3fce5400_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_compatible {"mmio-sram"}
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_IDX_0 "mmio-sram"
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_IDX_0_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fce5400, compatible, 0)
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fce5400, compatible, 0)
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fce5400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fce5400, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_3fce5400_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3fce5400_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3fce5400_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3fce5400_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3fce5400_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@3fcf0000
 *
 * Node identifier: DT_N_S_soc_S_memory_3fcf0000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3fcf0000_PATH "/soc/memory@3fcf0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3fcf0000_FULL_NAME "memory@3fcf0000"
#define DT_N_S_soc_S_memory_3fcf0000_FULL_NAME_UNQUOTED memory@3fcf0000
#define DT_N_S_soc_S_memory_3fcf0000_FULL_NAME_TOKEN memory_3fcf0000
#define DT_N_S_soc_S_memory_3fcf0000_FULL_NAME_UPPER_TOKEN MEMORY_3FCF0000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_3fcf0000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3fcf0000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3fcf0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_NODELABEL(fn) fn(sram2)
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram2, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3fcf0000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_3fcf0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_3fcf0000_HASH NKnNQ0S6nCfKDGsu2JCJzWz3KO4lwmSTxQ7YFL2YaIA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3fcf0000_ORD 53
#define DT_N_S_soc_S_memory_3fcf0000_ORD_STR_SORTABLE 00053

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3fcf0000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3fcf0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3fcf0000_EXISTS 1
#define DT_N_INST_4_zephyr_memory_region DT_N_S_soc_S_memory_3fcf0000
#define DT_N_INST_2_mmio_sram            DT_N_S_soc_S_memory_3fcf0000
#define DT_N_NODELABEL_sram2             DT_N_S_soc_S_memory_3fcf0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3fcf0000_REG_NUM 1
#define DT_N_S_soc_S_memory_3fcf0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_REG_IDX_0_VAL_ADDRESS 1070530560 /* 0x3fcf0000 */
#define DT_N_S_soc_S_memory_3fcf0000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_3fcf0000, 0)
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fcf0000, 0)
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fcf0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fcf0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3fcf0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3fcf0000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3fcf0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_3fcf0000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_3fcf0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3fcf0000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region "SRAM2"
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_STRING_UNQUOTED SRAM2
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_STRING_TOKEN SRAM2
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM2
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_IDX_0 "SRAM2"
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fcf0000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fcf0000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fcf0000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fcf0000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 1)
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 1)
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_3fcf0000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_3fcf0000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_reg {1070530560 /* 0x3fcf0000 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_memory_3fcf0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_reg_IDX_0 1070530560
#define DT_N_S_soc_S_memory_3fcf0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_reg_IDX_1 65536
#define DT_N_S_soc_S_memory_3fcf0000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3fcf0000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3fcf0000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@40370000
 *
 * Node identifier: DT_N_S_soc_S_memory_40370000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_40370000_PATH "/soc/memory@40370000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_40370000_FULL_NAME "memory@40370000"
#define DT_N_S_soc_S_memory_40370000_FULL_NAME_UNQUOTED memory@40370000
#define DT_N_S_soc_S_memory_40370000_FULL_NAME_TOKEN memory_40370000
#define DT_N_S_soc_S_memory_40370000_FULL_NAME_UPPER_TOKEN MEMORY_40370000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_40370000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_40370000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_40370000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_40370000_FOREACH_NODELABEL(fn) fn(sram0)
#define DT_N_S_soc_S_memory_40370000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sram0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_40370000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_40370000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_40370000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_40370000_HASH bOVAfly2sNW3W_XQpUFYqABhHFpTF6t1SKi4LCt6XeM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_40370000_ORD 54
#define DT_N_S_soc_S_memory_40370000_ORD_STR_SORTABLE 00054

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_40370000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_40370000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_40370000_EXISTS 1
#define DT_N_INST_2_zephyr_memory_region DT_N_S_soc_S_memory_40370000
#define DT_N_INST_0_mmio_sram            DT_N_S_soc_S_memory_40370000
#define DT_N_NODELABEL_sram0             DT_N_S_soc_S_memory_40370000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_40370000_REG_NUM 1
#define DT_N_S_soc_S_memory_40370000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_REG_IDX_0_VAL_ADDRESS 1077346304 /* 0x40370000 */
#define DT_N_S_soc_S_memory_40370000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_memory_40370000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_40370000, 0)
#define DT_N_S_soc_S_memory_40370000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40370000, 0)
#define DT_N_S_soc_S_memory_40370000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40370000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40370000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_40370000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_40370000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_40370000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_40370000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_40370000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_40370000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_40370000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_40370000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_40370000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region "SRAM0"
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_STRING_UNQUOTED SRAM0
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_STRING_TOKEN SRAM0
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM0
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_IDX_0 "SRAM0"
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40370000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40370000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40370000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40370000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_40370000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_40370000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_40370000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_40370000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_40370000, compatible, 1)
#define DT_N_S_soc_S_memory_40370000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_40370000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_40370000, compatible, 1)
#define DT_N_S_soc_S_memory_40370000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_40370000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_40370000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_40370000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_40370000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_40370000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_40370000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_reg {1077346304 /* 0x40370000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_memory_40370000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_reg_IDX_0 1077346304
#define DT_N_S_soc_S_memory_40370000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_memory_40370000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_40370000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_40370000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_40370000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_40370000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@42000000
 *
 * Node identifier: DT_N_S_soc_S_memory_42000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_42000000_PATH "/soc/memory@42000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_42000000_FULL_NAME "memory@42000000"
#define DT_N_S_soc_S_memory_42000000_FULL_NAME_UNQUOTED memory@42000000
#define DT_N_S_soc_S_memory_42000000_FULL_NAME_TOKEN memory_42000000
#define DT_N_S_soc_S_memory_42000000_FULL_NAME_UPPER_TOKEN MEMORY_42000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_42000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_42000000_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_42000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_42000000_FOREACH_NODELABEL(fn) fn(icache0)
#define DT_N_S_soc_S_memory_42000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(icache0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_42000000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_42000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_42000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_42000000_HASH MxgXaruz5v3eOd2Q__lowXsvExkVTFzT2vhBio8ss58

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_42000000_ORD 55
#define DT_N_S_soc_S_memory_42000000_ORD_STR_SORTABLE 00055

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_42000000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_42000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_42000000_EXISTS 1
#define DT_N_INST_0_zephyr_memory_region DT_N_S_soc_S_memory_42000000
#define DT_N_NODELABEL_icache0           DT_N_S_soc_S_memory_42000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_42000000_REG_NUM 1
#define DT_N_S_soc_S_memory_42000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_REG_IDX_0_VAL_ADDRESS 1107296256 /* 0x42000000 */
#define DT_N_S_soc_S_memory_42000000_REG_IDX_0_VAL_SIZE 33554432 /* 0x2000000 */
#define DT_N_S_soc_S_memory_42000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_42000000, 0)
#define DT_N_S_soc_S_memory_42000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_42000000, 0)
#define DT_N_S_soc_S_memory_42000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_42000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_42000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_42000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_42000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_42000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_42000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_42000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_42000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_42000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_42000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region "ICACHE0"
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_STRING_UNQUOTED ICACHE0
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_STRING_TOKEN ICACHE0
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_STRING_UPPER_TOKEN ICACHE0
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_IDX_0 "ICACHE0"
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_42000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_42000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_42000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_42000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_42000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_compatible {"zephyr,memory-region"}
#define DT_N_S_soc_S_memory_42000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_42000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_42000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_42000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_42000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_42000000, compatible, 0)
#define DT_N_S_soc_S_memory_42000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_42000000, compatible, 0)
#define DT_N_S_soc_S_memory_42000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_42000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_42000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_42000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_42000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_reg {1107296256 /* 0x42000000 */, 33554432 /* 0x2000000 */}
#define DT_N_S_soc_S_memory_42000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_reg_IDX_0 1107296256
#define DT_N_S_soc_S_memory_42000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_reg_IDX_1 33554432
#define DT_N_S_soc_S_memory_42000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_42000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_42000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_42000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_42000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@50000000
 *
 * Node identifier: DT_N_S_soc_S_memory_50000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_50000000_PATH "/soc/memory@50000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_50000000_FULL_NAME "memory@50000000"
#define DT_N_S_soc_S_memory_50000000_FULL_NAME_UNQUOTED memory@50000000
#define DT_N_S_soc_S_memory_50000000_FULL_NAME_TOKEN memory_50000000
#define DT_N_S_soc_S_memory_50000000_FULL_NAME_UPPER_TOKEN MEMORY_50000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_50000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_50000000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_50000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_50000000_FOREACH_NODELABEL(fn) fn(rtc_slow_ram)
#define DT_N_S_soc_S_memory_50000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc_slow_ram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_50000000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_50000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_50000000_HASH lOeq3apePEcrZ9bee_ko8WcMO3ecXZsFPMoWWQvHF2E

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_50000000_ORD 56
#define DT_N_S_soc_S_memory_50000000_ORD_STR_SORTABLE 00056

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_50000000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_50000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_50000000_EXISTS 1
#define DT_N_INST_5_zephyr_memory_region DT_N_S_soc_S_memory_50000000
#define DT_N_INST_5_mmio_sram            DT_N_S_soc_S_memory_50000000
#define DT_N_NODELABEL_rtc_slow_ram      DT_N_S_soc_S_memory_50000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_50000000_REG_NUM 1
#define DT_N_S_soc_S_memory_50000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */
#define DT_N_S_soc_S_memory_50000000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
#define DT_N_S_soc_S_memory_50000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_50000000, 0)
#define DT_N_S_soc_S_memory_50000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_50000000, 0)
#define DT_N_S_soc_S_memory_50000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_50000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_50000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_50000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_50000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_50000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_50000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_50000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_50000000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_50000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_50000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region "RTC_SLOW_RAM"
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_STRING_UNQUOTED RTC_SLOW_RAM
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_STRING_TOKEN RTC_SLOW_RAM
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_STRING_UPPER_TOKEN RTC_SLOW_RAM
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_IDX_0 "RTC_SLOW_RAM"
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_50000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_50000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_50000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_50000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_50000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_50000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_50000000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_50000000, compatible, 1)
#define DT_N_S_soc_S_memory_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_50000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_50000000, compatible, 1)
#define DT_N_S_soc_S_memory_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_50000000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_50000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_50000000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_50000000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_50000000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_50000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_reg {1342177280 /* 0x50000000 */, 8192 /* 0x2000 */}
#define DT_N_S_soc_S_memory_50000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_reg_IDX_0 1342177280
#define DT_N_S_soc_S_memory_50000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_reg_IDX_1 8192
#define DT_N_S_soc_S_memory_50000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_50000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_50000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_50000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@600fe000
 *
 * Node identifier: DT_N_S_soc_S_memory_600fe000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_600fe000_PATH "/soc/memory@600fe000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_600fe000_FULL_NAME "memory@600fe000"
#define DT_N_S_soc_S_memory_600fe000_FULL_NAME_UNQUOTED memory@600fe000
#define DT_N_S_soc_S_memory_600fe000_FULL_NAME_TOKEN memory_600fe000
#define DT_N_S_soc_S_memory_600fe000_FULL_NAME_UPPER_TOKEN MEMORY_600FE000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_600fe000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_600fe000_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_600fe000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_600fe000_FOREACH_NODELABEL(fn) fn(rtc_fast_ram)
#define DT_N_S_soc_S_memory_600fe000_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc_fast_ram, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_600fe000_CHILD_NUM 0
#define DT_N_S_soc_S_memory_600fe000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_600fe000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_600fe000_HASH OPeu87NduGo2caF08lYYkdtfy4uVXqUP5Rr0o3ibaR0

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_600fe000_ORD 57
#define DT_N_S_soc_S_memory_600fe000_ORD_STR_SORTABLE 00057

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_600fe000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_600fe000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_600fe000_EXISTS 1
#define DT_N_INST_6_zephyr_memory_region DT_N_S_soc_S_memory_600fe000
#define DT_N_INST_6_mmio_sram            DT_N_S_soc_S_memory_600fe000
#define DT_N_NODELABEL_rtc_fast_ram      DT_N_S_soc_S_memory_600fe000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_600fe000_REG_NUM 1
#define DT_N_S_soc_S_memory_600fe000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_REG_IDX_0_VAL_ADDRESS 1611653120 /* 0x600fe000 */
#define DT_N_S_soc_S_memory_600fe000_REG_IDX_0_VAL_SIZE 8192 /* 0x2000 */
#define DT_N_S_soc_S_memory_600fe000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_600fe000, 0)
#define DT_N_S_soc_S_memory_600fe000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_600fe000, 0)
#define DT_N_S_soc_S_memory_600fe000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_600fe000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_600fe000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_600fe000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_600fe000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_600fe000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_600fe000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_600fe000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_600fe000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_600fe000_COMPAT_MATCHES_mmio_sram 1
#define DT_N_S_soc_S_memory_600fe000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_600fe000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region "RTC_FAST_RAM"
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_STRING_UNQUOTED RTC_FAST_RAM
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_STRING_TOKEN RTC_FAST_RAM
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_STRING_UPPER_TOKEN RTC_FAST_RAM
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_IDX_0 "RTC_FAST_RAM"
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_600fe000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_600fe000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_600fe000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_600fe000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_compatible {"zephyr,memory-region", "mmio-sram"}
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_1 "mmio-sram"
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_1_STRING_TOKEN mmio_sram
#define DT_N_S_soc_S_memory_600fe000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM
#define DT_N_S_soc_S_memory_600fe000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_600fe000, compatible, 0) \
	fn(DT_N_S_soc_S_memory_600fe000, compatible, 1)
#define DT_N_S_soc_S_memory_600fe000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_600fe000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_600fe000, compatible, 1)
#define DT_N_S_soc_S_memory_600fe000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_600fe000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_memory_600fe000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_600fe000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_memory_600fe000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_memory_600fe000_P_compatible_LEN 2
#define DT_N_S_soc_S_memory_600fe000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_reg {1611653120 /* 0x600fe000 */, 8192 /* 0x2000 */}
#define DT_N_S_soc_S_memory_600fe000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_reg_IDX_0 1611653120
#define DT_N_S_soc_S_memory_600fe000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_reg_IDX_1 8192
#define DT_N_S_soc_S_memory_600fe000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_600fe000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_600fe000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/pcnt@60017000
 *
 * Node identifier: DT_N_S_soc_S_pcnt_60017000
 *
 * Binding (compatible = espressif,esp32-pcnt):
 *   $ZEPHYR_BASE/dts/bindings/sensor/espressif,esp32-pcnt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_pcnt_60017000_PATH "/soc/pcnt@60017000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_pcnt_60017000_FULL_NAME "pcnt@60017000"
#define DT_N_S_soc_S_pcnt_60017000_FULL_NAME_UNQUOTED pcnt@60017000
#define DT_N_S_soc_S_pcnt_60017000_FULL_NAME_TOKEN pcnt_60017000
#define DT_N_S_soc_S_pcnt_60017000_FULL_NAME_UPPER_TOKEN PCNT_60017000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_pcnt_60017000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_pcnt_60017000_CHILD_IDX 43

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_pcnt_60017000_NODELABEL_NUM 1
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_NODELABEL(fn) fn(pcnt)
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_NODELABEL_VARGS(fn, ...) fn(pcnt, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_pcnt_60017000_CHILD_NUM 0
#define DT_N_S_soc_S_pcnt_60017000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_pcnt_60017000_HASH ZClq9dISyBnVFDgypE61RUkaAu9k8TnnR9Ind07azs8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_pcnt_60017000_ORD 58
#define DT_N_S_soc_S_pcnt_60017000_ORD_STR_SORTABLE 00058

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_pcnt_60017000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_pcnt_60017000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_pcnt_60017000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_pcnt DT_N_S_soc_S_pcnt_60017000
#define DT_N_NODELABEL_pcnt              DT_N_S_soc_S_pcnt_60017000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_pcnt_60017000_REG_NUM 1
#define DT_N_S_soc_S_pcnt_60017000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_REG_IDX_0_VAL_ADDRESS 1610706944 /* 0x60017000 */
#define DT_N_S_soc_S_pcnt_60017000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_REG(fn) fn(DT_N_S_soc_S_pcnt_60017000, 0)
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, 0)
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_pcnt_60017000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pcnt_60017000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_RANGES_NUM 0
#define DT_N_S_soc_S_pcnt_60017000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_pcnt_60017000_IRQ_NUM 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_irq 41
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_pcnt_60017000_IRQ_LEVEL 1
#define DT_N_S_soc_S_pcnt_60017000_COMPAT_MATCHES_espressif_esp32_pcnt 1
#define DT_N_S_soc_S_pcnt_60017000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_pcnt_60017000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_COMPAT_MODEL_IDX_0 "esp32-pcnt"
#define DT_N_S_soc_S_pcnt_60017000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_pcnt_60017000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_pcnt_60017000_P_status "disabled"
#define DT_N_S_soc_S_pcnt_60017000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_pcnt_60017000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_pcnt_60017000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_pcnt_60017000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_pcnt_60017000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_pcnt_60017000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pcnt_60017000, status, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, status, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pcnt_60017000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pcnt_60017000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_status_LEN 1
#define DT_N_S_soc_S_pcnt_60017000_P_status_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_compatible {"espressif,esp32-pcnt"}
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_IDX_0 "espressif,esp32-pcnt"
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-pcnt
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_pcnt
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_PCNT
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pcnt_60017000, compatible, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, compatible, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pcnt_60017000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pcnt_60017000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_LEN 1
#define DT_N_S_soc_S_pcnt_60017000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_reg {1610706944 /* 0x60017000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_pcnt_60017000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_reg_IDX_0 1610706944
#define DT_N_S_soc_S_pcnt_60017000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_pcnt_60017000_P_reg_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts {41 /* 0x29 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_0 41
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_pcnt_60017000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pcnt_60017000, interrupt_parent, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, interrupt_parent, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pcnt_60017000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pcnt_60017000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_pcnt_60017000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_VAL_offset 113
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0, offset)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0, offset)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pcnt_60017000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_LEN 1
#define DT_N_S_soc_S_pcnt_60017000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_pcnt_60017000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_wakeup_source 0
#define DT_N_S_soc_S_pcnt_60017000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_pcnt_60017000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_pcnt_60017000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/rtc_timer@60008004
 *
 * Node identifier: DT_N_S_soc_S_rtc_timer_60008004
 *
 * Binding (compatible = espressif,esp32-rtc-timer):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-rtc-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_rtc_timer_60008004_PATH "/soc/rtc_timer@60008004"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_rtc_timer_60008004_FULL_NAME "rtc_timer@60008004"
#define DT_N_S_soc_S_rtc_timer_60008004_FULL_NAME_UNQUOTED rtc_timer@60008004
#define DT_N_S_soc_S_rtc_timer_60008004_FULL_NAME_TOKEN rtc_timer_60008004
#define DT_N_S_soc_S_rtc_timer_60008004_FULL_NAME_UPPER_TOKEN RTC_TIMER_60008004

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_rtc_timer_60008004_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_rtc_timer_60008004_CHILD_IDX 13

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_rtc_timer_60008004_NODELABEL_NUM 1
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_NODELABEL(fn) fn(rtc_timer)
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_NODELABEL_VARGS(fn, ...) fn(rtc_timer, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_rtc_timer_60008004_CHILD_NUM 0
#define DT_N_S_soc_S_rtc_timer_60008004_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_rtc_timer_60008004_HASH 4qN_L8f9vx8os_4o1HY0xZa_bIOyuYblmZLW1PIJL7Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_rtc_timer_60008004_ORD 59
#define DT_N_S_soc_S_rtc_timer_60008004_ORD_STR_SORTABLE 00059

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_rtc_timer_60008004_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_rtc_timer_60008004_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_rtc_timer_60008004_EXISTS 1
#define DT_N_INST_0_espressif_esp32_rtc_timer DT_N_S_soc_S_rtc_timer_60008004
#define DT_N_NODELABEL_rtc_timer              DT_N_S_soc_S_rtc_timer_60008004

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_rtc_timer_60008004_REG_NUM 1
#define DT_N_S_soc_S_rtc_timer_60008004_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_REG_IDX_0_VAL_ADDRESS 1610645508 /* 0x60008004 */
#define DT_N_S_soc_S_rtc_timer_60008004_REG_IDX_0_VAL_SIZE 12 /* 0xc */
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_REG(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_RANGES_NUM 0
#define DT_N_S_soc_S_rtc_timer_60008004_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_NUM 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_rtc_timer_60008004_IRQ_LEVEL 1
#define DT_N_S_soc_S_rtc_timer_60008004_COMPAT_MATCHES_espressif_esp32_rtc_timer 1
#define DT_N_S_soc_S_rtc_timer_60008004_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_rtc_timer_60008004_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_COMPAT_MODEL_IDX_0 "esp32-rtc-timer"
#define DT_N_S_soc_S_rtc_timer_60008004_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_rtc_timer_60008004_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_rtc_timer_60008004_P_status "disabled"
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, status, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, status, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_LEN 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_status_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible {"espressif,esp32-rtc-timer"}
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_IDX_0 "espressif,esp32-rtc-timer"
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-rtc-timer
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_rtc_timer
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_RTC_TIMER
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, compatible, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, compatible, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_LEN 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_compatible_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg {1610645508 /* 0x60008004 */, 12 /* 0xc */}
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg_IDX_0 1610645508
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg_IDX_1 12
#define DT_N_S_soc_S_rtc_timer_60008004_P_reg_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, interrupt_parent, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, interrupt_parent, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_VAL_offset 12
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0, offset)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0, offset)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_timer_60008004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_LEN 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_clocks_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_rtc_timer_60008004_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_wakeup_source 0
#define DT_N_S_soc_S_rtc_timer_60008004_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_rtc_timer_60008004_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_rtc_timer_60008004_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sha@6003b000
 *
 * Node identifier: DT_N_S_soc_S_sha_6003b000
 *
 * Binding (compatible = espressif,esp32-sha):
 *   $ZEPHYR_BASE/dts/bindings/crypto/espressif,esp32-sha.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sha_6003b000_PATH "/soc/sha@6003b000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sha_6003b000_FULL_NAME "sha@6003b000"
#define DT_N_S_soc_S_sha_6003b000_FULL_NAME_UNQUOTED sha@6003b000
#define DT_N_S_soc_S_sha_6003b000_FULL_NAME_TOKEN sha_6003b000
#define DT_N_S_soc_S_sha_6003b000_FULL_NAME_UPPER_TOKEN SHA_6003B000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sha_6003b000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sha_6003b000_CHILD_IDX 46

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sha_6003b000_NODELABEL_NUM 1
#define DT_N_S_soc_S_sha_6003b000_FOREACH_NODELABEL(fn) fn(sha)
#define DT_N_S_soc_S_sha_6003b000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sha, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sha_6003b000_CHILD_NUM 0
#define DT_N_S_soc_S_sha_6003b000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sha_6003b000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sha_6003b000_HASH 7OX0bTx4tdGa16cEdhK9sCwpllJb4Ei8sOPUFAW9i2o

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sha_6003b000_ORD 60
#define DT_N_S_soc_S_sha_6003b000_ORD_STR_SORTABLE 00060

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sha_6003b000_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sha_6003b000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sha_6003b000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_sha DT_N_S_soc_S_sha_6003b000
#define DT_N_NODELABEL_sha              DT_N_S_soc_S_sha_6003b000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sha_6003b000_REG_NUM 1
#define DT_N_S_soc_S_sha_6003b000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_REG_IDX_0_VAL_ADDRESS 1610854400 /* 0x6003b000 */
#define DT_N_S_soc_S_sha_6003b000_REG_IDX_0_VAL_SIZE 256 /* 0x100 */
#define DT_N_S_soc_S_sha_6003b000_FOREACH_REG(fn) fn(DT_N_S_soc_S_sha_6003b000, 0)
#define DT_N_S_soc_S_sha_6003b000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sha_6003b000, 0)
#define DT_N_S_soc_S_sha_6003b000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sha_6003b000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sha_6003b000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_RANGES_NUM 0
#define DT_N_S_soc_S_sha_6003b000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sha_6003b000_IRQ_NUM 0
#define DT_N_S_soc_S_sha_6003b000_IRQ_LEVEL 0
#define DT_N_S_soc_S_sha_6003b000_COMPAT_MATCHES_espressif_esp32_sha 1
#define DT_N_S_soc_S_sha_6003b000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_sha_6003b000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_COMPAT_MODEL_IDX_0 "esp32-sha"
#define DT_N_S_soc_S_sha_6003b000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sha_6003b000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sha_6003b000_P_status "okay"
#define DT_N_S_soc_S_sha_6003b000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_sha_6003b000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_sha_6003b000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_sha_6003b000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_sha_6003b000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_sha_6003b000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sha_6003b000, status, 0)
#define DT_N_S_soc_S_sha_6003b000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sha_6003b000, status, 0)
#define DT_N_S_soc_S_sha_6003b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sha_6003b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sha_6003b000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_status_LEN 1
#define DT_N_S_soc_S_sha_6003b000_P_status_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_compatible {"espressif,esp32-sha"}
#define DT_N_S_soc_S_sha_6003b000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_compatible_IDX_0 "espressif,esp32-sha"
#define DT_N_S_soc_S_sha_6003b000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-sha
#define DT_N_S_soc_S_sha_6003b000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_sha
#define DT_N_S_soc_S_sha_6003b000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SHA
#define DT_N_S_soc_S_sha_6003b000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sha_6003b000, compatible, 0)
#define DT_N_S_soc_S_sha_6003b000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sha_6003b000, compatible, 0)
#define DT_N_S_soc_S_sha_6003b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sha_6003b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sha_6003b000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_compatible_LEN 1
#define DT_N_S_soc_S_sha_6003b000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_reg {1610854400 /* 0x6003b000 */, 256 /* 0x100 */}
#define DT_N_S_soc_S_sha_6003b000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_reg_IDX_0 1610854400
#define DT_N_S_soc_S_sha_6003b000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_reg_IDX_1 256
#define DT_N_S_soc_S_sha_6003b000_P_reg_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_VAL_offset 122
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0, offset)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0, offset)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_sha_6003b000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sha_6003b000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sha_6003b000_P_clocks_LEN 1
#define DT_N_S_soc_S_sha_6003b000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sha_6003b000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_wakeup_source 0
#define DT_N_S_soc_S_sha_6003b000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sha_6003b000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sha_6003b000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@60025000
 *
 * Node identifier: DT_N_S_soc_S_spi_60025000
 *
 * Binding (compatible = espressif,esp32-spi):
 *   $ZEPHYR_BASE/dts/bindings/spi/espressif,esp32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_60025000_PATH "/soc/spi@60025000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_60025000_FULL_NAME "spi@60025000"
#define DT_N_S_soc_S_spi_60025000_FULL_NAME_UNQUOTED spi@60025000
#define DT_N_S_soc_S_spi_60025000_FULL_NAME_TOKEN spi_60025000
#define DT_N_S_soc_S_spi_60025000_FULL_NAME_UPPER_TOKEN SPI_60025000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_60025000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_60025000_CHILD_IDX 25

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_60025000_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_60025000_FOREACH_NODELABEL(fn) fn(spi3)
#define DT_N_S_soc_S_spi_60025000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi3, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_60025000_CHILD_NUM 0
#define DT_N_S_soc_S_spi_60025000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_60025000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_60025000_HASH AznhjxWB4dhjf4qM0h7xJWMCnW1aYspNqC8gyq4ldGM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_60025000_ORD 61
#define DT_N_S_soc_S_spi_60025000_ORD_STR_SORTABLE 00061

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_60025000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_60025000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_60025000_EXISTS 1
#define DT_N_INST_1_espressif_esp32_spi DT_N_S_soc_S_spi_60025000
#define DT_N_NODELABEL_spi3             DT_N_S_soc_S_spi_60025000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_60025000_REG_NUM 1
#define DT_N_S_soc_S_spi_60025000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_REG_IDX_0_VAL_ADDRESS 1610764288 /* 0x60025000 */
#define DT_N_S_soc_S_spi_60025000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_60025000_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_60025000, 0)
#define DT_N_S_soc_S_spi_60025000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, 0)
#define DT_N_S_soc_S_spi_60025000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60025000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60025000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_60025000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_60025000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_irq 22
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60025000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_60025000_COMPAT_MATCHES_espressif_esp32_spi 1
#define DT_N_S_soc_S_spi_60025000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_spi_60025000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_COMPAT_MODEL_IDX_0 "esp32-spi"
#define DT_N_S_soc_S_spi_60025000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_60025000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_60025000_P_reg {1610764288 /* 0x60025000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_60025000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_reg_IDX_0 1610764288
#define DT_N_S_soc_S_spi_60025000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_60025000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_half_duplex 0
#define DT_N_S_soc_S_spi_60025000_P_half_duplex_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_dummy_comp 0
#define DT_N_S_soc_S_spi_60025000_P_dummy_comp_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_sio 0
#define DT_N_S_soc_S_spi_60025000_P_sio_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_dma_enabled 0
#define DT_N_S_soc_S_spi_60025000_P_dma_enabled_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_dma_host 1
#define DT_N_S_soc_S_spi_60025000_P_dma_host_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_clk_as_cs 0
#define DT_N_S_soc_S_spi_60025000_P_clk_as_cs_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_positive_cs 0
#define DT_N_S_soc_S_spi_60025000_P_positive_cs_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_use_iomux 0
#define DT_N_S_soc_S_spi_60025000_P_use_iomux_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_line_idle_low 0
#define DT_N_S_soc_S_spi_60025000_P_line_idle_low_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_status "disabled"
#define DT_N_S_soc_S_spi_60025000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_spi_60025000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_spi_60025000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_spi_60025000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_spi_60025000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_spi_60025000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60025000, status, 0)
#define DT_N_S_soc_S_spi_60025000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, status, 0)
#define DT_N_S_soc_S_spi_60025000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60025000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60025000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_status_LEN 1
#define DT_N_S_soc_S_spi_60025000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_compatible {"espressif,esp32-spi"}
#define DT_N_S_soc_S_spi_60025000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_compatible_IDX_0 "espressif,esp32-spi"
#define DT_N_S_soc_S_spi_60025000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-spi
#define DT_N_S_soc_S_spi_60025000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_spi
#define DT_N_S_soc_S_spi_60025000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SPI
#define DT_N_S_soc_S_spi_60025000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60025000, compatible, 0)
#define DT_N_S_soc_S_spi_60025000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, compatible, 0)
#define DT_N_S_soc_S_spi_60025000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60025000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60025000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_60025000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupts {22 /* 0x16 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_0 22
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_spi_60025000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60025000, interrupt_parent, 0)
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, interrupt_parent, 0)
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60025000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60025000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_spi_60025000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_VAL_offset 116
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60025000, clocks, 0, offset)
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, clocks, 0, offset)
#define DT_N_S_soc_S_spi_60025000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_spi_60025000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60025000, clocks, 0)
#define DT_N_S_soc_S_spi_60025000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60025000, clocks, 0)
#define DT_N_S_soc_S_spi_60025000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60025000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60025000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60025000_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_60025000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_60025000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_60025000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_60025000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_60025000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/touch@6000885c
 *
 * Node identifier: DT_N_S_soc_S_touch_6000885c
 *
 * Binding (compatible = espressif,esp32-touch):
 *   $ZEPHYR_BASE/dts/bindings/input/espressif,esp32-touch.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_touch_6000885c_PATH "/soc/touch@6000885c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_touch_6000885c_FULL_NAME "touch@6000885c"
#define DT_N_S_soc_S_touch_6000885c_FULL_NAME_UNQUOTED touch@6000885c
#define DT_N_S_soc_S_touch_6000885c_FULL_NAME_TOKEN touch_6000885c
#define DT_N_S_soc_S_touch_6000885c_FULL_NAME_UPPER_TOKEN TOUCH_6000885C

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_touch_6000885c_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_touch_6000885c_CHILD_IDX 19

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_touch_6000885c_NODELABEL_NUM 1
#define DT_N_S_soc_S_touch_6000885c_FOREACH_NODELABEL(fn) fn(touch)
#define DT_N_S_soc_S_touch_6000885c_FOREACH_NODELABEL_VARGS(fn, ...) fn(touch, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_touch_6000885c_CHILD_NUM 0
#define DT_N_S_soc_S_touch_6000885c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_touch_6000885c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_touch_6000885c_HASH lW5T4xPXuGhuol5FH_i1tsfAufZ7rqCd0mYWu_aMCLA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_touch_6000885c_ORD 62
#define DT_N_S_soc_S_touch_6000885c_ORD_STR_SORTABLE 00062

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_touch_6000885c_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_touch_6000885c_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_touch_6000885c_EXISTS 1
#define DT_N_INST_0_espressif_esp32_touch DT_N_S_soc_S_touch_6000885c
#define DT_N_NODELABEL_touch              DT_N_S_soc_S_touch_6000885c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_touch_6000885c_REG_NUM 2
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_0_VAL_ADDRESS 1610647644 /* 0x6000885c */
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_0_VAL_SIZE 136 /* 0x88 */
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_1_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_1_VAL_ADDRESS 1610647816 /* 0x60008908 */
#define DT_N_S_soc_S_touch_6000885c_REG_IDX_1_VAL_SIZE 24 /* 0x18 */
#define DT_N_S_soc_S_touch_6000885c_FOREACH_REG(fn) fn(DT_N_S_soc_S_touch_6000885c, 0) fn(DT_N_S_soc_S_touch_6000885c, 1)
#define DT_N_S_soc_S_touch_6000885c_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_touch_6000885c, 0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_touch_6000885c, 1)
#define DT_N_S_soc_S_touch_6000885c_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_touch_6000885c, 0, __VA_ARGS__) fn(DT_N_S_soc_S_touch_6000885c, 1, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_touch_6000885c, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_touch_6000885c, 1, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_RANGES_NUM 0
#define DT_N_S_soc_S_touch_6000885c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_touch_6000885c_IRQ_NUM 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_touch_6000885c_IRQ_LEVEL 1
#define DT_N_S_soc_S_touch_6000885c_COMPAT_MATCHES_espressif_esp32_touch 1
#define DT_N_S_soc_S_touch_6000885c_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_touch_6000885c_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_COMPAT_MODEL_IDX_0 "esp32-touch"
#define DT_N_S_soc_S_touch_6000885c_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_touch_6000885c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_touch_6000885c_P_debounce_interval_ms 30
#define DT_N_S_soc_S_touch_6000885c_P_debounce_interval_ms_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt 2700000
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt_IDX_0_ENUM_VAL_2700000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt_ENUM_VAL_2700000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_microvolt_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt 500000
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt_IDX_0_ENUM_VAL_500000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt_ENUM_VAL_500000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_lref_microvolt_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt 1000000
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt_IDX_0_ENUM_VAL_1000000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt_ENUM_VAL_1000000_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_href_atten_microvolt_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_mode 2
#define DT_N_S_soc_S_touch_6000885c_P_filter_mode_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_debounce_cnt 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_debounce_cnt_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_noise_thr 0
#define DT_N_S_soc_S_touch_6000885c_P_filter_noise_thr_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_jitter_step 4
#define DT_N_S_soc_S_touch_6000885c_P_filter_jitter_step_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_smooth_level 1
#define DT_N_S_soc_S_touch_6000885c_P_filter_smooth_level_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_status "disabled"
#define DT_N_S_soc_S_touch_6000885c_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_touch_6000885c_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_touch_6000885c_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_touch_6000885c_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_touch_6000885c_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_touch_6000885c_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_touch_6000885c, status, 0)
#define DT_N_S_soc_S_touch_6000885c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_touch_6000885c, status, 0)
#define DT_N_S_soc_S_touch_6000885c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_touch_6000885c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_touch_6000885c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_status_LEN 1
#define DT_N_S_soc_S_touch_6000885c_P_status_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_compatible {"espressif,esp32-touch"}
#define DT_N_S_soc_S_touch_6000885c_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_compatible_IDX_0 "espressif,esp32-touch"
#define DT_N_S_soc_S_touch_6000885c_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-touch
#define DT_N_S_soc_S_touch_6000885c_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_touch
#define DT_N_S_soc_S_touch_6000885c_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TOUCH
#define DT_N_S_soc_S_touch_6000885c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_touch_6000885c, compatible, 0)
#define DT_N_S_soc_S_touch_6000885c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_touch_6000885c, compatible, 0)
#define DT_N_S_soc_S_touch_6000885c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_touch_6000885c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_touch_6000885c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_compatible_LEN 1
#define DT_N_S_soc_S_touch_6000885c_P_compatible_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_reg {1610647644 /* 0x6000885c */, 136 /* 0x88 */, 1610647816 /* 0x60008908 */, 24 /* 0x18 */}
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_0 1610647644
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_1 136
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_2_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_2 1610647816
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_3_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_reg_IDX_3 24
#define DT_N_S_soc_S_touch_6000885c_P_reg_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_touch_6000885c_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_touch_6000885c, interrupt_parent, 0)
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_touch_6000885c, interrupt_parent, 0)
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_touch_6000885c, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_touch_6000885c, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_touch_6000885c_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_touch_6000885c_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_wakeup_source 0
#define DT_N_S_soc_S_touch_6000885c_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_touch_6000885c_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_touch_6000885c_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/trng@6003507c
 *
 * Node identifier: DT_N_S_soc_S_trng_6003507c
 *
 * Binding (compatible = espressif,esp32-trng):
 *   $ZEPHYR_BASE/dts/bindings/rng/espressif,esp32-trng.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_trng_6003507c_PATH "/soc/trng@6003507c"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_trng_6003507c_FULL_NAME "trng@6003507c"
#define DT_N_S_soc_S_trng_6003507c_FULL_NAME_UNQUOTED trng@6003507c
#define DT_N_S_soc_S_trng_6003507c_FULL_NAME_TOKEN trng_6003507c
#define DT_N_S_soc_S_trng_6003507c_FULL_NAME_UPPER_TOKEN TRNG_6003507C

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_trng_6003507c_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_trng_6003507c_CHILD_IDX 39

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_trng_6003507c_NODELABEL_NUM 1
#define DT_N_S_soc_S_trng_6003507c_FOREACH_NODELABEL(fn) fn(trng0)
#define DT_N_S_soc_S_trng_6003507c_FOREACH_NODELABEL_VARGS(fn, ...) fn(trng0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_trng_6003507c_CHILD_NUM 0
#define DT_N_S_soc_S_trng_6003507c_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_trng_6003507c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_trng_6003507c_HASH HC97_ePl1pevUbx8SWLgTpeKRqKtqSyA_b3OchELVbI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_trng_6003507c_ORD 63
#define DT_N_S_soc_S_trng_6003507c_ORD_STR_SORTABLE 00063

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_trng_6003507c_REQUIRES_ORDS \
	12, /* /soc */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_trng_6003507c_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_trng_6003507c_EXISTS 1
#define DT_N_INST_0_espressif_esp32_trng DT_N_S_soc_S_trng_6003507c
#define DT_N_NODELABEL_trng0             DT_N_S_soc_S_trng_6003507c

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_trng_6003507c_REG_NUM 1
#define DT_N_S_soc_S_trng_6003507c_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_REG_IDX_0_VAL_ADDRESS 1610829948 /* 0x6003507c */
#define DT_N_S_soc_S_trng_6003507c_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_trng_6003507c_FOREACH_REG(fn) fn(DT_N_S_soc_S_trng_6003507c, 0)
#define DT_N_S_soc_S_trng_6003507c_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_trng_6003507c, 0)
#define DT_N_S_soc_S_trng_6003507c_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_trng_6003507c, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_trng_6003507c, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_RANGES_NUM 0
#define DT_N_S_soc_S_trng_6003507c_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_trng_6003507c_IRQ_NUM 0
#define DT_N_S_soc_S_trng_6003507c_IRQ_LEVEL 0
#define DT_N_S_soc_S_trng_6003507c_COMPAT_MATCHES_espressif_esp32_trng 1
#define DT_N_S_soc_S_trng_6003507c_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_trng_6003507c_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_COMPAT_MODEL_IDX_0 "esp32-trng"
#define DT_N_S_soc_S_trng_6003507c_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_trng_6003507c_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_trng_6003507c_P_reg {1610829948 /* 0x6003507c */, 4 /* 0x4 */}
#define DT_N_S_soc_S_trng_6003507c_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_reg_IDX_0 1610829948
#define DT_N_S_soc_S_trng_6003507c_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_reg_IDX_1 4
#define DT_N_S_soc_S_trng_6003507c_P_reg_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_status "okay"
#define DT_N_S_soc_S_trng_6003507c_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_trng_6003507c_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_trng_6003507c_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_trng_6003507c_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_trng_6003507c_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_trng_6003507c_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_trng_6003507c, status, 0)
#define DT_N_S_soc_S_trng_6003507c_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_trng_6003507c, status, 0)
#define DT_N_S_soc_S_trng_6003507c_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_trng_6003507c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_trng_6003507c, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_status_LEN 1
#define DT_N_S_soc_S_trng_6003507c_P_status_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_compatible {"espressif,esp32-trng"}
#define DT_N_S_soc_S_trng_6003507c_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_compatible_IDX_0 "espressif,esp32-trng"
#define DT_N_S_soc_S_trng_6003507c_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-trng
#define DT_N_S_soc_S_trng_6003507c_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_trng
#define DT_N_S_soc_S_trng_6003507c_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TRNG
#define DT_N_S_soc_S_trng_6003507c_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_trng_6003507c, compatible, 0)
#define DT_N_S_soc_S_trng_6003507c_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_trng_6003507c, compatible, 0)
#define DT_N_S_soc_S_trng_6003507c_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_trng_6003507c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_trng_6003507c, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_compatible_LEN 1
#define DT_N_S_soc_S_trng_6003507c_P_compatible_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_VAL_offset 6
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0, offset)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0, offset)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_trng_6003507c_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_trng_6003507c, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_trng_6003507c_P_clocks_LEN 1
#define DT_N_S_soc_S_trng_6003507c_P_clocks_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_trng_6003507c_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_wakeup_source 0
#define DT_N_S_soc_S_trng_6003507c_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_trng_6003507c_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_trng_6003507c_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/uart@60000000
 *
 * Node identifier: DT_N_S_soc_S_uart_60000000
 *
 * Binding (compatible = espressif,esp32-uart):
 *   $ZEPHYR_BASE/dts/bindings/serial/espressif,esp32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_60000000_PATH "/soc/uart@60000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_60000000_FULL_NAME "uart@60000000"
#define DT_N_S_soc_S_uart_60000000_FULL_NAME_UNQUOTED uart@60000000
#define DT_N_S_soc_S_uart_60000000_FULL_NAME_TOKEN uart_60000000
#define DT_N_S_soc_S_uart_60000000_FULL_NAME_UPPER_TOKEN UART_60000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_60000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_60000000_CHILD_IDX 15

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_uart_60000000_NODELABEL_NUM 2
#define DT_N_S_soc_S_uart_60000000_FOREACH_NODELABEL(fn) fn(uart0) fn(xiao_serial)
#define DT_N_S_soc_S_uart_60000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart0, __VA_ARGS__) fn(xiao_serial, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_60000000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_60000000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_uart_60000000_HASH D2t8eqRVs7EeMF7E6_m3Gv7t97nd7h5PH0XDmtUvrbk

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_60000000_ORD 64
#define DT_N_S_soc_S_uart_60000000_ORD_STR_SORTABLE 00064

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_60000000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	31, /* /pin-controller/uart0_default */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_60000000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_60000000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_uart DT_N_S_soc_S_uart_60000000
#define DT_N_NODELABEL_uart0             DT_N_S_soc_S_uart_60000000
#define DT_N_NODELABEL_xiao_serial       DT_N_S_soc_S_uart_60000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_60000000_REG_NUM 1
#define DT_N_S_soc_S_uart_60000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_REG_IDX_0_VAL_ADDRESS 1610612736 /* 0x60000000 */
#define DT_N_S_soc_S_uart_60000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_60000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_uart_60000000, 0)
#define DT_N_S_soc_S_uart_60000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, 0)
#define DT_N_S_soc_S_uart_60000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_60000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_60000000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_irq 27
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60000000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_60000000_COMPAT_MATCHES_espressif_esp32_uart 1
#define DT_N_S_soc_S_uart_60000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_uart_60000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_COMPAT_MODEL_IDX_0 "esp32-uart"
#define DT_N_S_soc_S_uart_60000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_60000000_PINCTRL_NUM 1
#define DT_N_S_soc_S_uart_60000000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_uart_60000000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_60000000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_uart_60000000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_uart0_default

/* Generic property macros: */
#define DT_N_S_soc_S_uart_60000000_P_reg {1610612736 /* 0x60000000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_60000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_reg_IDX_0 1610612736
#define DT_N_S_soc_S_uart_60000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_60000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_uart0_default
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, pinctrl_0, 0)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, pinctrl_names, 0)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, pinctrl_names, 0)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits "1"
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, stop_bits, 0)
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, stop_bits, 0)
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_data_bits 8
#define DT_N_S_soc_S_uart_60000000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_uart_60000000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_hw_rs485_hd_mode 0
#define DT_N_S_soc_S_uart_60000000_P_hw_rs485_hd_mode_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_uhci_slip_tx 0
#define DT_N_S_soc_S_uart_60000000_P_uhci_slip_tx_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_uhci_slip_rx 0
#define DT_N_S_soc_S_uart_60000000_P_uhci_slip_rx_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_current_speed 115200
#define DT_N_S_soc_S_uart_60000000_P_current_speed_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_60000000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_parity "none"
#define DT_N_S_soc_S_uart_60000000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_uart_60000000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_uart_60000000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_uart_60000000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_uart_60000000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_60000000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, parity, 0)
#define DT_N_S_soc_S_uart_60000000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, parity, 0)
#define DT_N_S_soc_S_uart_60000000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_parity_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_parity_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_status "okay"
#define DT_N_S_soc_S_uart_60000000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_uart_60000000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uart_60000000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uart_60000000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_uart_60000000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_60000000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, status, 0)
#define DT_N_S_soc_S_uart_60000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, status, 0)
#define DT_N_S_soc_S_uart_60000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_status_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_compatible {"espressif,esp32-uart"}
#define DT_N_S_soc_S_uart_60000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_compatible_IDX_0 "espressif,esp32-uart"
#define DT_N_S_soc_S_uart_60000000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-uart
#define DT_N_S_soc_S_uart_60000000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_uart
#define DT_N_S_soc_S_uart_60000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_UART
#define DT_N_S_soc_S_uart_60000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, compatible, 0)
#define DT_N_S_soc_S_uart_60000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, compatible, 0)
#define DT_N_S_soc_S_uart_60000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupts {27 /* 0x1b */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_0 27
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_uart_60000000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_VAL_offset 101
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_uart_60000000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60000000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_uart_60000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60000000, clocks, 0)
#define DT_N_S_soc_S_uart_60000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60000000, clocks, 0)
#define DT_N_S_soc_S_uart_60000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60000000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60000000_P_clocks_LEN 1
#define DT_N_S_soc_S_uart_60000000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_60000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_60000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_60000000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_tx_invert 0
#define DT_N_S_soc_S_uart_60000000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_uart_60000000_P_rx_invert 0
#define DT_N_S_soc_S_uart_60000000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/uart@60010000
 *
 * Node identifier: DT_N_S_soc_S_uart_60010000
 *
 * Binding (compatible = espressif,esp32-uart):
 *   $ZEPHYR_BASE/dts/bindings/serial/espressif,esp32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_60010000_PATH "/soc/uart@60010000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_60010000_FULL_NAME "uart@60010000"
#define DT_N_S_soc_S_uart_60010000_FULL_NAME_UNQUOTED uart@60010000
#define DT_N_S_soc_S_uart_60010000_FULL_NAME_TOKEN uart_60010000
#define DT_N_S_soc_S_uart_60010000_FULL_NAME_UPPER_TOKEN UART_60010000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_60010000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_60010000_CHILD_IDX 16

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_uart_60010000_NODELABEL_NUM 1
#define DT_N_S_soc_S_uart_60010000_FOREACH_NODELABEL(fn) fn(uart1)
#define DT_N_S_soc_S_uart_60010000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart1, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_60010000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_60010000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60010000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_uart_60010000_HASH OkwyyZMwHXXvX_HFm8OAnDn4_hvWBRFy2cOSz91fWpo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_60010000_ORD 65
#define DT_N_S_soc_S_uart_60010000_ORD_STR_SORTABLE 00065

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_60010000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_60010000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_60010000_EXISTS 1
#define DT_N_INST_1_espressif_esp32_uart DT_N_S_soc_S_uart_60010000
#define DT_N_NODELABEL_uart1             DT_N_S_soc_S_uart_60010000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_60010000_REG_NUM 1
#define DT_N_S_soc_S_uart_60010000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_REG_IDX_0_VAL_ADDRESS 1610678272 /* 0x60010000 */
#define DT_N_S_soc_S_uart_60010000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_60010000_FOREACH_REG(fn) fn(DT_N_S_soc_S_uart_60010000, 0)
#define DT_N_S_soc_S_uart_60010000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, 0)
#define DT_N_S_soc_S_uart_60010000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_60010000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_60010000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_irq 28
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60010000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_60010000_COMPAT_MATCHES_espressif_esp32_uart 1
#define DT_N_S_soc_S_uart_60010000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_uart_60010000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_COMPAT_MODEL_IDX_0 "esp32-uart"
#define DT_N_S_soc_S_uart_60010000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_60010000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uart_60010000_P_reg {1610678272 /* 0x60010000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_60010000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_reg_IDX_0 1610678272
#define DT_N_S_soc_S_uart_60010000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_60010000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits "1"
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, stop_bits, 0)
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, stop_bits, 0)
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_data_bits 8
#define DT_N_S_soc_S_uart_60010000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_uart_60010000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_hw_rs485_hd_mode 0
#define DT_N_S_soc_S_uart_60010000_P_hw_rs485_hd_mode_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_uhci_slip_tx 0
#define DT_N_S_soc_S_uart_60010000_P_uhci_slip_tx_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_uhci_slip_rx 0
#define DT_N_S_soc_S_uart_60010000_P_uhci_slip_rx_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_60010000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_parity "none"
#define DT_N_S_soc_S_uart_60010000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_uart_60010000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_uart_60010000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_uart_60010000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_uart_60010000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_60010000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, parity, 0)
#define DT_N_S_soc_S_uart_60010000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, parity, 0)
#define DT_N_S_soc_S_uart_60010000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_parity_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_parity_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_status "disabled"
#define DT_N_S_soc_S_uart_60010000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_uart_60010000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_uart_60010000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_uart_60010000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_uart_60010000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_uart_60010000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, status, 0)
#define DT_N_S_soc_S_uart_60010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, status, 0)
#define DT_N_S_soc_S_uart_60010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_status_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_compatible {"espressif,esp32-uart"}
#define DT_N_S_soc_S_uart_60010000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_compatible_IDX_0 "espressif,esp32-uart"
#define DT_N_S_soc_S_uart_60010000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-uart
#define DT_N_S_soc_S_uart_60010000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_uart
#define DT_N_S_soc_S_uart_60010000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_UART
#define DT_N_S_soc_S_uart_60010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, compatible, 0)
#define DT_N_S_soc_S_uart_60010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, compatible, 0)
#define DT_N_S_soc_S_uart_60010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupts {28 /* 0x1c */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_0 28
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_uart_60010000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_VAL_offset 0
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_uart_60010000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60010000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_uart_60010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60010000, clocks, 0)
#define DT_N_S_soc_S_uart_60010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60010000, clocks, 0)
#define DT_N_S_soc_S_uart_60010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60010000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60010000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60010000_P_clocks_LEN 1
#define DT_N_S_soc_S_uart_60010000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_60010000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_60010000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_60010000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_tx_invert 0
#define DT_N_S_soc_S_uart_60010000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_uart_60010000_P_rx_invert 0
#define DT_N_S_soc_S_uart_60010000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/uart@6002e000
 *
 * Node identifier: DT_N_S_soc_S_uart_6002e000
 *
 * Binding (compatible = espressif,esp32-uart):
 *   $ZEPHYR_BASE/dts/bindings/serial/espressif,esp32-uart.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_6002e000_PATH "/soc/uart@6002e000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_6002e000_FULL_NAME "uart@6002e000"
#define DT_N_S_soc_S_uart_6002e000_FULL_NAME_UNQUOTED uart@6002e000
#define DT_N_S_soc_S_uart_6002e000_FULL_NAME_TOKEN uart_6002e000
#define DT_N_S_soc_S_uart_6002e000_FULL_NAME_UPPER_TOKEN UART_6002E000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_6002e000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_6002e000_CHILD_IDX 17

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_uart_6002e000_NODELABEL_NUM 1
#define DT_N_S_soc_S_uart_6002e000_FOREACH_NODELABEL(fn) fn(uart2)
#define DT_N_S_soc_S_uart_6002e000_FOREACH_NODELABEL_VARGS(fn, ...) fn(uart2, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_6002e000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_6002e000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_6002e000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_uart_6002e000_HASH CfJ0T6fz61kURKSrb0v66avgdgV4kuF8h1pW_ibpPbc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_6002e000_ORD 66
#define DT_N_S_soc_S_uart_6002e000_ORD_STR_SORTABLE 00066

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_6002e000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_6002e000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_6002e000_EXISTS 1
#define DT_N_INST_2_espressif_esp32_uart DT_N_S_soc_S_uart_6002e000
#define DT_N_NODELABEL_uart2             DT_N_S_soc_S_uart_6002e000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_6002e000_REG_NUM 1
#define DT_N_S_soc_S_uart_6002e000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_REG_IDX_0_VAL_ADDRESS 1610801152 /* 0x6002e000 */
#define DT_N_S_soc_S_uart_6002e000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_6002e000_FOREACH_REG(fn) fn(DT_N_S_soc_S_uart_6002e000, 0)
#define DT_N_S_soc_S_uart_6002e000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, 0)
#define DT_N_S_soc_S_uart_6002e000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_6002e000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_6002e000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_irq 29
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_6002e000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_6002e000_COMPAT_MATCHES_espressif_esp32_uart 1
#define DT_N_S_soc_S_uart_6002e000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_uart_6002e000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_COMPAT_MODEL_IDX_0 "esp32-uart"
#define DT_N_S_soc_S_uart_6002e000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_6002e000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uart_6002e000_P_reg {1610801152 /* 0x6002e000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_6002e000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_reg_IDX_0 1610801152
#define DT_N_S_soc_S_uart_6002e000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_6002e000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits "1"
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_STRING_UNQUOTED 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_STRING_TOKEN 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_STRING_UPPER_TOKEN 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_IDX_0 "1"
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, stop_bits, 0)
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, stop_bits, 0)
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, stop_bits, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_stop_bits_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_data_bits 8
#define DT_N_S_soc_S_uart_6002e000_P_data_bits_IDX_0_ENUM_IDX 3
#define DT_N_S_soc_S_uart_6002e000_P_data_bits_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_data_bits_IDX_0_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_data_bits_ENUM_VAL_8_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_data_bits_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_hw_rs485_hd_mode 0
#define DT_N_S_soc_S_uart_6002e000_P_hw_rs485_hd_mode_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_uhci_slip_tx 0
#define DT_N_S_soc_S_uart_6002e000_P_uhci_slip_tx_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_uhci_slip_rx 0
#define DT_N_S_soc_S_uart_6002e000_P_uhci_slip_rx_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_6002e000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_parity "none"
#define DT_N_S_soc_S_uart_6002e000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_uart_6002e000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_uart_6002e000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_uart_6002e000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_uart_6002e000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_6002e000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, parity, 0)
#define DT_N_S_soc_S_uart_6002e000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, parity, 0)
#define DT_N_S_soc_S_uart_6002e000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_parity_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_parity_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_status "disabled"
#define DT_N_S_soc_S_uart_6002e000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_uart_6002e000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_uart_6002e000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_uart_6002e000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_uart_6002e000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_uart_6002e000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, status, 0)
#define DT_N_S_soc_S_uart_6002e000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, status, 0)
#define DT_N_S_soc_S_uart_6002e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_status_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_compatible {"espressif,esp32-uart"}
#define DT_N_S_soc_S_uart_6002e000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_compatible_IDX_0 "espressif,esp32-uart"
#define DT_N_S_soc_S_uart_6002e000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-uart
#define DT_N_S_soc_S_uart_6002e000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_uart
#define DT_N_S_soc_S_uart_6002e000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_UART
#define DT_N_S_soc_S_uart_6002e000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, compatible, 0)
#define DT_N_S_soc_S_uart_6002e000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, compatible, 0)
#define DT_N_S_soc_S_uart_6002e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupts {29 /* 0x1d */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_0 29
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_uart_6002e000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_VAL_offset 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_6002e000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_6002e000_P_clocks_LEN 1
#define DT_N_S_soc_S_uart_6002e000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_6002e000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_6002e000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_6002e000_P_zephyr_pm_device_runtime_auto_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_tx_invert 0
#define DT_N_S_soc_S_uart_6002e000_P_tx_invert_EXISTS 1
#define DT_N_S_soc_S_uart_6002e000_P_rx_invert 0
#define DT_N_S_soc_S_uart_6002e000_P_rx_invert_EXISTS 1

/*
 * Devicetree node: /soc/uart@60038000
 *
 * Node identifier: DT_N_S_soc_S_uart_60038000
 *
 * Binding (compatible = espressif,esp32-usb-serial):
 *   $ZEPHYR_BASE/dts/bindings/serial/espressif,esp32-usb-serial.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_uart_60038000_PATH "/soc/uart@60038000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_uart_60038000_FULL_NAME "uart@60038000"
#define DT_N_S_soc_S_uart_60038000_FULL_NAME_UNQUOTED uart@60038000
#define DT_N_S_soc_S_uart_60038000_FULL_NAME_TOKEN uart_60038000
#define DT_N_S_soc_S_uart_60038000_FULL_NAME_UPPER_TOKEN UART_60038000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_uart_60038000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_uart_60038000_CHILD_IDX 31

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_uart_60038000_NODELABEL_NUM 1
#define DT_N_S_soc_S_uart_60038000_FOREACH_NODELABEL(fn) fn(usb_serial)
#define DT_N_S_soc_S_uart_60038000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb_serial, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_uart_60038000_CHILD_NUM 0
#define DT_N_S_soc_S_uart_60038000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_uart_60038000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_uart_60038000_HASH i55DjZv1Mym_Gwy1kdlGQYS_Iy3G4lHZXW__C0ktZe8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_uart_60038000_ORD 67
#define DT_N_S_soc_S_uart_60038000_ORD_STR_SORTABLE 00067

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_uart_60038000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_uart_60038000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_uart_60038000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_usb_serial DT_N_S_soc_S_uart_60038000
#define DT_N_NODELABEL_usb_serial              DT_N_S_soc_S_uart_60038000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_uart_60038000_REG_NUM 1
#define DT_N_S_soc_S_uart_60038000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_REG_IDX_0_VAL_ADDRESS 1610842112 /* 0x60038000 */
#define DT_N_S_soc_S_uart_60038000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_uart_60038000_FOREACH_REG(fn) fn(DT_N_S_soc_S_uart_60038000, 0)
#define DT_N_S_soc_S_uart_60038000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, 0)
#define DT_N_S_soc_S_uart_60038000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_RANGES_NUM 0
#define DT_N_S_soc_S_uart_60038000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_uart_60038000_IRQ_NUM 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_irq 96
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60038000_IRQ_LEVEL 1
#define DT_N_S_soc_S_uart_60038000_COMPAT_MATCHES_espressif_esp32_usb_serial 1
#define DT_N_S_soc_S_uart_60038000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_uart_60038000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_COMPAT_MODEL_IDX_0 "esp32-usb-serial"
#define DT_N_S_soc_S_uart_60038000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_uart_60038000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_uart_60038000_P_reg {1610842112 /* 0x60038000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_uart_60038000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_reg_IDX_0 1610842112
#define DT_N_S_soc_S_uart_60038000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_uart_60038000_P_reg_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_hw_flow_control 0
#define DT_N_S_soc_S_uart_60038000_P_hw_flow_control_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_parity "none"
#define DT_N_S_soc_S_uart_60038000_P_parity_STRING_UNQUOTED none
#define DT_N_S_soc_S_uart_60038000_P_parity_STRING_TOKEN none
#define DT_N_S_soc_S_uart_60038000_P_parity_STRING_UPPER_TOKEN NONE
#define DT_N_S_soc_S_uart_60038000_P_parity_IDX_0 "none"
#define DT_N_S_soc_S_uart_60038000_P_parity_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_parity_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_60038000_P_parity_IDX_0_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_parity_ENUM_VAL_none_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_parity_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60038000, parity, 0)
#define DT_N_S_soc_S_uart_60038000_P_parity_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, parity, 0)
#define DT_N_S_soc_S_uart_60038000_P_parity_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_parity_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, parity, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_parity_LEN 1
#define DT_N_S_soc_S_uart_60038000_P_parity_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_status "okay"
#define DT_N_S_soc_S_uart_60038000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_uart_60038000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_uart_60038000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_uart_60038000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_uart_60038000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_uart_60038000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60038000, status, 0)
#define DT_N_S_soc_S_uart_60038000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, status, 0)
#define DT_N_S_soc_S_uart_60038000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_status_LEN 1
#define DT_N_S_soc_S_uart_60038000_P_status_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_compatible {"espressif,esp32-usb-serial"}
#define DT_N_S_soc_S_uart_60038000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_compatible_IDX_0 "espressif,esp32-usb-serial"
#define DT_N_S_soc_S_uart_60038000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-usb-serial
#define DT_N_S_soc_S_uart_60038000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_usb_serial
#define DT_N_S_soc_S_uart_60038000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_USB_SERIAL
#define DT_N_S_soc_S_uart_60038000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60038000, compatible, 0)
#define DT_N_S_soc_S_uart_60038000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, compatible, 0)
#define DT_N_S_soc_S_uart_60038000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_compatible_LEN 1
#define DT_N_S_soc_S_uart_60038000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupts {96 /* 0x60 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_0 96
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_uart_60038000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60038000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, interrupt_parent, 0)
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_uart_60038000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_VAL_offset 102
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_uart_60038000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, clocks, 0, offset)
#define DT_N_S_soc_S_uart_60038000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_uart_60038000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_uart_60038000, clocks, 0)
#define DT_N_S_soc_S_uart_60038000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_uart_60038000, clocks, 0)
#define DT_N_S_soc_S_uart_60038000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_uart_60038000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_uart_60038000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_uart_60038000_P_clocks_LEN 1
#define DT_N_S_soc_S_uart_60038000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_uart_60038000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_wakeup_source 0
#define DT_N_S_soc_S_uart_60038000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_uart_60038000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_uart_60038000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/usb_otg@60080000
 *
 * Node identifier: DT_N_S_soc_S_usb_otg_60080000
 *
 * Binding (compatible = espressif,esp32-usb-otg):
 *   $ZEPHYR_BASE/dts/bindings/usb/espressif,esp32-usb-otg.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_usb_otg_60080000_PATH "/soc/usb_otg@60080000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_usb_otg_60080000_FULL_NAME "usb_otg@60080000"
#define DT_N_S_soc_S_usb_otg_60080000_FULL_NAME_UNQUOTED usb_otg@60080000
#define DT_N_S_soc_S_usb_otg_60080000_FULL_NAME_TOKEN usb_otg_60080000
#define DT_N_S_soc_S_usb_otg_60080000_FULL_NAME_UPPER_TOKEN USB_OTG_60080000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_usb_otg_60080000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_usb_otg_60080000_CHILD_IDX 32

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_usb_otg_60080000_NODELABEL_NUM 1
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_NODELABEL(fn) fn(usb_otg)
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_NODELABEL_VARGS(fn, ...) fn(usb_otg, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_usb_otg_60080000_CHILD_NUM 0
#define DT_N_S_soc_S_usb_otg_60080000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_usb_otg_60080000_HASH PNZSl3Hk_XMxv3clTQft8QkalCAra1lAUWIxqMgf0xA

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_usb_otg_60080000_ORD 68
#define DT_N_S_soc_S_usb_otg_60080000_ORD_STR_SORTABLE 00068

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_usb_otg_60080000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_usb_otg_60080000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_usb_otg_60080000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_usb_otg DT_N_S_soc_S_usb_otg_60080000
#define DT_N_INST_0_snps_dwc2               DT_N_S_soc_S_usb_otg_60080000
#define DT_N_NODELABEL_usb_otg              DT_N_S_soc_S_usb_otg_60080000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_usb_otg_60080000_REG_NUM 1
#define DT_N_S_soc_S_usb_otg_60080000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_REG_IDX_0_VAL_ADDRESS 1611137024 /* 0x60080000 */
#define DT_N_S_soc_S_usb_otg_60080000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_REG(fn) fn(DT_N_S_soc_S_usb_otg_60080000, 0)
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, 0)
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_otg_60080000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_otg_60080000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_RANGES_NUM 0
#define DT_N_S_soc_S_usb_otg_60080000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_NUM 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_irq 38
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_usb_otg_60080000_IRQ_LEVEL 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MATCHES_espressif_esp32_usb_otg 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MODEL_IDX_0 "esp32-usb-otg"
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MATCHES_snps_dwc2 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_VENDOR_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_VENDOR_IDX_1 "Synopsys, Inc."
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MODEL_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_COMPAT_MODEL_IDX_1 "dwc2"
#define DT_N_S_soc_S_usb_otg_60080000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_usb_otg_60080000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_VAL_offset 102
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0, offset)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0, offset)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_otg_60080000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_LEN 1
#define DT_N_S_soc_S_usb_otg_60080000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_reg {1611137024 /* 0x60080000 */, 262144 /* 0x40000 */}
#define DT_N_S_soc_S_usb_otg_60080000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_reg_IDX_0 1611137024
#define DT_N_S_soc_S_usb_otg_60080000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_reg_IDX_1 262144
#define DT_N_S_soc_S_usb_otg_60080000_P_reg_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts {38 /* 0x26 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_0 38
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_num_in_eps 6
#define DT_N_S_soc_S_usb_otg_60080000_P_num_in_eps_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_num_out_eps 6
#define DT_N_S_soc_S_usb_otg_60080000_P_num_out_eps_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg1 0
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg2 575527216
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg2_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg4 3555762224
#define DT_N_S_soc_S_usb_otg_60080000_P_ghwcfg4_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status "disabled"
#define DT_N_S_soc_S_usb_otg_60080000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_usb_otg_60080000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_usb_otg_60080000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_usb_otg_60080000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_usb_otg_60080000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_otg_60080000, status, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, status, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_otg_60080000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_otg_60080000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_status_LEN 1
#define DT_N_S_soc_S_usb_otg_60080000_P_status_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible {"espressif,esp32-usb-otg", "snps,dwc2"}
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_0 "espressif,esp32-usb-otg"
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-usb-otg
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_usb_otg
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_USB_OTG
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_1_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_1 "snps,dwc2"
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_1_STRING_UNQUOTED snps,dwc2
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_1_STRING_TOKEN snps_dwc2
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_IDX_1_STRING_UPPER_TOKEN SNPS_DWC2
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 0) \
	fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 1)
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 1)
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_usb_otg_60080000, compatible, 1, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_LEN 2
#define DT_N_S_soc_S_usb_otg_60080000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_otg_60080000, interrupt_parent, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_otg_60080000, interrupt_parent, 0)
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_otg_60080000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_otg_60080000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_usb_otg_60080000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_usb_otg_60080000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_wakeup_source 0
#define DT_N_S_soc_S_usb_otg_60080000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_usb_otg_60080000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_usb_otg_60080000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@6001f048
 *
 * Node identifier: DT_N_S_soc_S_watchdog_6001f048
 *
 * Binding (compatible = espressif,esp32-watchdog):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_6001f048_PATH "/soc/watchdog@6001f048"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_6001f048_FULL_NAME "watchdog@6001f048"
#define DT_N_S_soc_S_watchdog_6001f048_FULL_NAME_UNQUOTED watchdog@6001f048
#define DT_N_S_soc_S_watchdog_6001f048_FULL_NAME_TOKEN watchdog_6001f048
#define DT_N_S_soc_S_watchdog_6001f048_FULL_NAME_UPPER_TOKEN WATCHDOG_6001F048

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_6001f048_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_6001f048_CHILD_IDX 37

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_6001f048_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_NODELABEL(fn) fn(wdt0)
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_6001f048_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_6001f048_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_6001f048_HASH DWmLPdAAzCqaMJiM_4ieP1Itac7FFBT5sXrLyDShxp4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_6001f048_ORD 69
#define DT_N_S_soc_S_watchdog_6001f048_ORD_STR_SORTABLE 00069

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_6001f048_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_6001f048_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_6001f048_EXISTS 1
#define DT_N_ALIAS_watchdog0                 DT_N_S_soc_S_watchdog_6001f048
#define DT_N_INST_0_espressif_esp32_watchdog DT_N_S_soc_S_watchdog_6001f048
#define DT_N_NODELABEL_wdt0                  DT_N_S_soc_S_watchdog_6001f048

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_6001f048_REG_NUM 1
#define DT_N_S_soc_S_watchdog_6001f048_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_REG_IDX_0_VAL_ADDRESS 1610739784 /* 0x6001f048 */
#define DT_N_S_soc_S_watchdog_6001f048_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_6001f048, 0)
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, 0)
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_6001f048, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_6001f048_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_irq 52
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_6001f048_IRQ_LEVEL 1
#define DT_N_S_soc_S_watchdog_6001f048_COMPAT_MATCHES_espressif_esp32_watchdog 1
#define DT_N_S_soc_S_watchdog_6001f048_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_watchdog_6001f048_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_COMPAT_MODEL_IDX_0 "esp32-watchdog"
#define DT_N_S_soc_S_watchdog_6001f048_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_6001f048_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_6001f048_P_reg {1610739784 /* 0x6001f048 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_watchdog_6001f048_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_reg_IDX_0 1610739784
#define DT_N_S_soc_S_watchdog_6001f048_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_reg_IDX_1 32
#define DT_N_S_soc_S_watchdog_6001f048_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_status "okay"
#define DT_N_S_soc_S_watchdog_6001f048_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_watchdog_6001f048_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_watchdog_6001f048_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_watchdog_6001f048_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_watchdog_6001f048_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_watchdog_6001f048_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_6001f048, status, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, status, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_6001f048, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_6001f048_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible {"espressif,esp32-watchdog"}
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_IDX_0 "espressif,esp32-watchdog"
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-watchdog
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_watchdog
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_WATCHDOG
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_6001f048, compatible, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, compatible, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_6001f048, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_6001f048_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts {52 /* 0x34 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_0 52
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_6001f048, interrupt_parent, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, interrupt_parent, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_6001f048, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_watchdog_6001f048_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_VAL_offset 3
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0, offset)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0, offset)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_6001f048, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_LEN 1
#define DT_N_S_soc_S_watchdog_6001f048_P_clocks_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_6001f048_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_6001f048_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_6001f048_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_6001f048_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/watchdog@60020048
 *
 * Node identifier: DT_N_S_soc_S_watchdog_60020048
 *
 * Binding (compatible = espressif,esp32-watchdog):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_watchdog_60020048_PATH "/soc/watchdog@60020048"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_watchdog_60020048_FULL_NAME "watchdog@60020048"
#define DT_N_S_soc_S_watchdog_60020048_FULL_NAME_UNQUOTED watchdog@60020048
#define DT_N_S_soc_S_watchdog_60020048_FULL_NAME_TOKEN watchdog_60020048
#define DT_N_S_soc_S_watchdog_60020048_FULL_NAME_UPPER_TOKEN WATCHDOG_60020048

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_watchdog_60020048_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_watchdog_60020048_CHILD_IDX 38

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_watchdog_60020048_NODELABEL_NUM 1
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_NODELABEL(fn) fn(wdt1)
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_NODELABEL_VARGS(fn, ...) fn(wdt1, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_watchdog_60020048_CHILD_NUM 0
#define DT_N_S_soc_S_watchdog_60020048_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_watchdog_60020048_HASH dYcqxfqxhKDdp5Wc7WZNv_6Q6eeOHnvANXhuU6BI3Z4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_watchdog_60020048_ORD 70
#define DT_N_S_soc_S_watchdog_60020048_ORD_STR_SORTABLE 00070

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_watchdog_60020048_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_watchdog_60020048_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_watchdog_60020048_EXISTS 1
#define DT_N_INST_1_espressif_esp32_watchdog DT_N_S_soc_S_watchdog_60020048
#define DT_N_NODELABEL_wdt1                  DT_N_S_soc_S_watchdog_60020048

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_watchdog_60020048_REG_NUM 1
#define DT_N_S_soc_S_watchdog_60020048_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_REG_IDX_0_VAL_ADDRESS 1610743880 /* 0x60020048 */
#define DT_N_S_soc_S_watchdog_60020048_REG_IDX_0_VAL_SIZE 32 /* 0x20 */
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_REG(fn) fn(DT_N_S_soc_S_watchdog_60020048, 0)
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, 0)
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_60020048, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_60020048, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_RANGES_NUM 0
#define DT_N_S_soc_S_watchdog_60020048_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_watchdog_60020048_IRQ_NUM 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_irq 55
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_60020048_IRQ_LEVEL 1
#define DT_N_S_soc_S_watchdog_60020048_COMPAT_MATCHES_espressif_esp32_watchdog 1
#define DT_N_S_soc_S_watchdog_60020048_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_watchdog_60020048_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_COMPAT_MODEL_IDX_0 "esp32-watchdog"
#define DT_N_S_soc_S_watchdog_60020048_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_watchdog_60020048_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_watchdog_60020048_P_reg {1610743880 /* 0x60020048 */, 32 /* 0x20 */}
#define DT_N_S_soc_S_watchdog_60020048_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_reg_IDX_0 1610743880
#define DT_N_S_soc_S_watchdog_60020048_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_reg_IDX_1 32
#define DT_N_S_soc_S_watchdog_60020048_P_reg_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_status "disabled"
#define DT_N_S_soc_S_watchdog_60020048_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_watchdog_60020048_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_watchdog_60020048_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_watchdog_60020048_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_watchdog_60020048_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_watchdog_60020048_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_60020048, status, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, status, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_60020048, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_60020048, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_status_LEN 1
#define DT_N_S_soc_S_watchdog_60020048_P_status_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_compatible {"espressif,esp32-watchdog"}
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_IDX_0 "espressif,esp32-watchdog"
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-watchdog
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_watchdog
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_WATCHDOG
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_60020048, compatible, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, compatible, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_60020048, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_60020048, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_LEN 1
#define DT_N_S_soc_S_watchdog_60020048_P_compatible_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts {55 /* 0x37 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_0 55
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_watchdog_60020048_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_60020048, interrupt_parent, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, interrupt_parent, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_60020048, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_60020048, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_watchdog_60020048_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_VAL_offset 4
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0, offset)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0, offset)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_60020048, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_LEN 1
#define DT_N_S_soc_S_watchdog_60020048_P_clocks_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_watchdog_60020048_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_wakeup_source 0
#define DT_N_S_soc_S_watchdog_60020048_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_watchdog_60020048_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_watchdog_60020048_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/xt_wdt@60021004
 *
 * Node identifier: DT_N_S_soc_S_xt_wdt_60021004
 *
 * Binding (compatible = espressif,esp32-xt-wdt):
 *   $ZEPHYR_BASE/dts/bindings/watchdog/espressif,esp32-xt-wdt.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_xt_wdt_60021004_PATH "/soc/xt_wdt@60021004"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_xt_wdt_60021004_FULL_NAME "xt_wdt@60021004"
#define DT_N_S_soc_S_xt_wdt_60021004_FULL_NAME_UNQUOTED xt_wdt@60021004
#define DT_N_S_soc_S_xt_wdt_60021004_FULL_NAME_TOKEN xt_wdt_60021004
#define DT_N_S_soc_S_xt_wdt_60021004_FULL_NAME_UPPER_TOKEN XT_WDT_60021004

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_xt_wdt_60021004_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_xt_wdt_60021004_CHILD_IDX 12

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_xt_wdt_60021004_NODELABEL_NUM 1
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_NODELABEL(fn) fn(xt_wdt)
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_NODELABEL_VARGS(fn, ...) fn(xt_wdt, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_xt_wdt_60021004_CHILD_NUM 0
#define DT_N_S_soc_S_xt_wdt_60021004_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_xt_wdt_60021004_HASH LbgBebYRgPg030SGlIcQbCaWYeKTWouWYWvBH4ADkdY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_xt_wdt_60021004_ORD 71
#define DT_N_S_soc_S_xt_wdt_60021004_ORD_STR_SORTABLE 00071

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_xt_wdt_60021004_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_xt_wdt_60021004_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_xt_wdt_60021004_EXISTS 1
#define DT_N_INST_0_espressif_esp32_xt_wdt DT_N_S_soc_S_xt_wdt_60021004
#define DT_N_NODELABEL_xt_wdt              DT_N_S_soc_S_xt_wdt_60021004

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_xt_wdt_60021004_REG_NUM 1
#define DT_N_S_soc_S_xt_wdt_60021004_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_REG_IDX_0_VAL_ADDRESS 1610747908 /* 0x60021004 */
#define DT_N_S_soc_S_xt_wdt_60021004_REG_IDX_0_VAL_SIZE 4 /* 0x4 */
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_REG(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_RANGES_NUM 0
#define DT_N_S_soc_S_xt_wdt_60021004_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_NUM 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_irq 39
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_xt_wdt_60021004_IRQ_LEVEL 1
#define DT_N_S_soc_S_xt_wdt_60021004_COMPAT_MATCHES_espressif_esp32_xt_wdt 1
#define DT_N_S_soc_S_xt_wdt_60021004_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_xt_wdt_60021004_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_COMPAT_MODEL_IDX_0 "esp32-xt-wdt"
#define DT_N_S_soc_S_xt_wdt_60021004_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_xt_wdt_60021004_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg {1610747908 /* 0x60021004 */, 4 /* 0x4 */}
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg_IDX_0 1610747908
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg_IDX_1 4
#define DT_N_S_soc_S_xt_wdt_60021004_P_reg_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status "disabled"
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, status, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, status, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_LEN 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_status_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible {"espressif,esp32-xt-wdt"}
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_IDX_0 "espressif,esp32-xt-wdt"
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-xt-wdt
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_xt_wdt
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_XT_WDT
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, compatible, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, compatible, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_LEN 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_compatible_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_0 39
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, interrupt_parent, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, interrupt_parent, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_VAL_offset 12
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0, offset)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0, offset)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_xt_wdt_60021004, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_LEN 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_clocks_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_xt_wdt_60021004_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_wakeup_source 0
#define DT_N_S_soc_S_xt_wdt_60021004_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_xt_wdt_60021004_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_xt_wdt_60021004_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@6001f000
 *
 * Node identifier: DT_N_S_soc_S_counter_6001f000
 *
 * Binding (compatible = espressif,esp32-timer):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_6001f000_PATH "/soc/counter@6001f000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_6001f000_FULL_NAME "counter@6001f000"
#define DT_N_S_soc_S_counter_6001f000_FULL_NAME_UNQUOTED counter@6001f000
#define DT_N_S_soc_S_counter_6001f000_FULL_NAME_TOKEN counter_6001f000
#define DT_N_S_soc_S_counter_6001f000_FULL_NAME_UPPER_TOKEN COUNTER_6001F000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_counter_6001f000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_6001f000_CHILD_IDX 33

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_6001f000_NODELABEL_NUM 1
#define DT_N_S_soc_S_counter_6001f000_FOREACH_NODELABEL(fn) fn(timer0)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_6001f000_CHILD_NUM 1
#define DT_N_S_soc_S_counter_6001f000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_counter_6001f000_S_counter)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000_S_counter)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_6001f000_HASH Rrs5kpmU6w_9iEjhLyqLTIL2mlU51fBWqnVs1LhbFsc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_6001f000_ORD 72
#define DT_N_S_soc_S_counter_6001f000_ORD_STR_SORTABLE 00072

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_6001f000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_6001f000_SUPPORTS_ORDS \
	73, /* /soc/counter@6001f000/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_6001f000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_timer DT_N_S_soc_S_counter_6001f000
#define DT_N_NODELABEL_timer0             DT_N_S_soc_S_counter_6001f000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_6001f000_REG_NUM 1
#define DT_N_S_soc_S_counter_6001f000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_REG_IDX_0_VAL_ADDRESS 1610739712 /* 0x6001f000 */
#define DT_N_S_soc_S_counter_6001f000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_counter_6001f000_FOREACH_REG(fn) fn(DT_N_S_soc_S_counter_6001f000, 0)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, 0)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_RANGES_NUM 0
#define DT_N_S_soc_S_counter_6001f000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_6001f000_IRQ_NUM 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_irq 50
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f000_IRQ_LEVEL 1
#define DT_N_S_soc_S_counter_6001f000_COMPAT_MATCHES_espressif_esp32_timer 1
#define DT_N_S_soc_S_counter_6001f000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_6001f000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_COMPAT_MODEL_IDX_0 "esp32-timer"
#define DT_N_S_soc_S_counter_6001f000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_6001f000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_6001f000_P_group 0
#define DT_N_S_soc_S_counter_6001f000_P_group_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_6001f000_P_group_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_group_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_group_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_group_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_index 0
#define DT_N_S_soc_S_counter_6001f000_P_index_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_6001f000_P_index_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_index_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_index_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_index_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_prescaler 2
#define DT_N_S_soc_S_counter_6001f000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_status "okay"
#define DT_N_S_soc_S_counter_6001f000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_counter_6001f000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_counter_6001f000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_counter_6001f000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_counter_6001f000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_6001f000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000, status, 0)
#define DT_N_S_soc_S_counter_6001f000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, status, 0)
#define DT_N_S_soc_S_counter_6001f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_status_LEN 1
#define DT_N_S_soc_S_counter_6001f000_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_compatible {"espressif,esp32-timer"}
#define DT_N_S_soc_S_counter_6001f000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_compatible_IDX_0 "espressif,esp32-timer"
#define DT_N_S_soc_S_counter_6001f000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-timer
#define DT_N_S_soc_S_counter_6001f000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_timer
#define DT_N_S_soc_S_counter_6001f000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TIMER
#define DT_N_S_soc_S_counter_6001f000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000, compatible, 0)
#define DT_N_S_soc_S_counter_6001f000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, compatible, 0)
#define DT_N_S_soc_S_counter_6001f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_6001f000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_reg {1610739712 /* 0x6001f000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_counter_6001f000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_reg_IDX_0 1610739712
#define DT_N_S_soc_S_counter_6001f000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_counter_6001f000_P_reg_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupts {50 /* 0x32 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_0 50
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_counter_6001f000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_counter_6001f000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_VAL_offset 3
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0, offset)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0, offset)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_counter_6001f000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_P_clocks_LEN 1
#define DT_N_S_soc_S_counter_6001f000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_6001f000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_wakeup_source 0
#define DT_N_S_soc_S_counter_6001f000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_6001f000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@6001f000/counter
 *
 * Node identifier: DT_N_S_soc_S_counter_6001f000_S_counter
 *
 * Binding (compatible = espressif,esp32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_PATH "/soc/counter@6001f000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_counter_6001f000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_counter_6001f000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_counter_6001f000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/counter@6001f000) identifier: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_PARENT DT_N_S_soc_S_counter_6001f000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_6001f000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_HASH 1BnW7PebcpbOj6PyPgfIKSK7qnhKCToBNW9fE9PQyjI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_ORD 73
#define DT_N_S_soc_S_counter_6001f000_S_counter_ORD_STR_SORTABLE 00073

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_REQUIRES_ORDS \
	72, /* /soc/counter@6001f000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_EXISTS 1
#define DT_N_INST_0_espressif_esp32_counter DT_N_S_soc_S_counter_6001f000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_6001f000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_COMPAT_MATCHES_espressif_esp32_counter 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_6001f000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_COMPAT_MODEL_IDX_0 "esp32-counter"
#define DT_N_S_soc_S_counter_6001f000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000_S_counter, status, 0)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000_S_counter, status, 0)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible {"espressif,esp32-counter"}
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_IDX_0 "espressif,esp32-counter"
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-counter
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_counter
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_COUNTER
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f000_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f000_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_6001f000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@6001f024
 *
 * Node identifier: DT_N_S_soc_S_counter_6001f024
 *
 * Binding (compatible = espressif,esp32-timer):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_6001f024_PATH "/soc/counter@6001f024"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_6001f024_FULL_NAME "counter@6001f024"
#define DT_N_S_soc_S_counter_6001f024_FULL_NAME_UNQUOTED counter@6001f024
#define DT_N_S_soc_S_counter_6001f024_FULL_NAME_TOKEN counter_6001f024
#define DT_N_S_soc_S_counter_6001f024_FULL_NAME_UPPER_TOKEN COUNTER_6001F024

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_counter_6001f024_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_6001f024_CHILD_IDX 34

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_6001f024_NODELABEL_NUM 1
#define DT_N_S_soc_S_counter_6001f024_FOREACH_NODELABEL(fn) fn(timer1)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer1, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_6001f024_CHILD_NUM 1
#define DT_N_S_soc_S_counter_6001f024_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_counter_6001f024_S_counter)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024_S_counter)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f024_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_6001f024_HASH _tHOMBth7FeWlv20MFmpXa9YUGYxsPx0aNQxZBF_J0w

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_6001f024_ORD 74
#define DT_N_S_soc_S_counter_6001f024_ORD_STR_SORTABLE 00074

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_6001f024_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_6001f024_SUPPORTS_ORDS \
	75, /* /soc/counter@6001f024/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_6001f024_EXISTS 1
#define DT_N_INST_1_espressif_esp32_timer DT_N_S_soc_S_counter_6001f024
#define DT_N_NODELABEL_timer1             DT_N_S_soc_S_counter_6001f024

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_6001f024_REG_NUM 1
#define DT_N_S_soc_S_counter_6001f024_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_REG_IDX_0_VAL_ADDRESS 1610739748 /* 0x6001f024 */
#define DT_N_S_soc_S_counter_6001f024_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_counter_6001f024_FOREACH_REG(fn) fn(DT_N_S_soc_S_counter_6001f024, 0)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, 0)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_RANGES_NUM 0
#define DT_N_S_soc_S_counter_6001f024_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_6001f024_IRQ_NUM 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_irq 51
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f024_IRQ_LEVEL 1
#define DT_N_S_soc_S_counter_6001f024_COMPAT_MATCHES_espressif_esp32_timer 1
#define DT_N_S_soc_S_counter_6001f024_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_6001f024_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_COMPAT_MODEL_IDX_0 "esp32-timer"
#define DT_N_S_soc_S_counter_6001f024_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_6001f024_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_6001f024_P_group 0
#define DT_N_S_soc_S_counter_6001f024_P_group_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_6001f024_P_group_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_group_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_group_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_group_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_index 1
#define DT_N_S_soc_S_counter_6001f024_P_index_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_6001f024_P_index_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_index_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_index_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_index_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_prescaler 2
#define DT_N_S_soc_S_counter_6001f024_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_status "okay"
#define DT_N_S_soc_S_counter_6001f024_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_counter_6001f024_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_counter_6001f024_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_counter_6001f024_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_counter_6001f024_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_6001f024_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024, status, 0)
#define DT_N_S_soc_S_counter_6001f024_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, status, 0)
#define DT_N_S_soc_S_counter_6001f024_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_status_LEN 1
#define DT_N_S_soc_S_counter_6001f024_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_compatible {"espressif,esp32-timer"}
#define DT_N_S_soc_S_counter_6001f024_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_compatible_IDX_0 "espressif,esp32-timer"
#define DT_N_S_soc_S_counter_6001f024_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-timer
#define DT_N_S_soc_S_counter_6001f024_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_timer
#define DT_N_S_soc_S_counter_6001f024_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TIMER
#define DT_N_S_soc_S_counter_6001f024_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024, compatible, 0)
#define DT_N_S_soc_S_counter_6001f024_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, compatible, 0)
#define DT_N_S_soc_S_counter_6001f024_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_6001f024_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_reg {1610739748 /* 0x6001f024 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_counter_6001f024_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_reg_IDX_0 1610739748
#define DT_N_S_soc_S_counter_6001f024_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_reg_IDX_1 4096
#define DT_N_S_soc_S_counter_6001f024_P_reg_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_0 51
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_counter_6001f024_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_counter_6001f024_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_VAL_offset 3
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0, offset)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0, offset)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_counter_6001f024_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_P_clocks_LEN 1
#define DT_N_S_soc_S_counter_6001f024_P_clocks_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_6001f024_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_wakeup_source 0
#define DT_N_S_soc_S_counter_6001f024_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_6001f024_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@6001f024/counter
 *
 * Node identifier: DT_N_S_soc_S_counter_6001f024_S_counter
 *
 * Binding (compatible = espressif,esp32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_PATH "/soc/counter@6001f024/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_counter_6001f024_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_counter_6001f024_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_counter_6001f024_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/counter@6001f024) identifier: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_PARENT DT_N_S_soc_S_counter_6001f024

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_6001f024_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_HASH fwggem_m4lB1Y0CWaSxY44D8ApJMgGzNwFwYBLnBeFI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_ORD 75
#define DT_N_S_soc_S_counter_6001f024_S_counter_ORD_STR_SORTABLE 00075

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_REQUIRES_ORDS \
	74, /* /soc/counter@6001f024 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_EXISTS 1
#define DT_N_INST_1_espressif_esp32_counter DT_N_S_soc_S_counter_6001f024_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_REG_NUM 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_6001f024_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_COMPAT_MATCHES_espressif_esp32_counter 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_6001f024_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_COMPAT_MODEL_IDX_0 "esp32-counter"
#define DT_N_S_soc_S_counter_6001f024_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status "disabled"
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024_S_counter, status, 0)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024_S_counter, status, 0)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible {"espressif,esp32-counter"}
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_IDX_0 "espressif,esp32-counter"
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-counter
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_counter
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_COUNTER
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_6001f024_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_6001f024_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_6001f024_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_6001f024_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@60020000
 *
 * Node identifier: DT_N_S_soc_S_counter_60020000
 *
 * Binding (compatible = espressif,esp32-timer):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_60020000_PATH "/soc/counter@60020000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_60020000_FULL_NAME "counter@60020000"
#define DT_N_S_soc_S_counter_60020000_FULL_NAME_UNQUOTED counter@60020000
#define DT_N_S_soc_S_counter_60020000_FULL_NAME_TOKEN counter_60020000
#define DT_N_S_soc_S_counter_60020000_FULL_NAME_UPPER_TOKEN COUNTER_60020000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_counter_60020000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_60020000_CHILD_IDX 35

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_60020000_NODELABEL_NUM 1
#define DT_N_S_soc_S_counter_60020000_FOREACH_NODELABEL(fn) fn(timer2)
#define DT_N_S_soc_S_counter_60020000_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer2, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_60020000_CHILD_NUM 1
#define DT_N_S_soc_S_counter_60020000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_counter_60020000_S_counter)
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000_S_counter)
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_60020000_HASH xCx78bIBDOX3I64HiTwhWz_zp_ta0pfUDZNQ0MGTKxo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_60020000_ORD 76
#define DT_N_S_soc_S_counter_60020000_ORD_STR_SORTABLE 00076

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_60020000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_60020000_SUPPORTS_ORDS \
	77, /* /soc/counter@60020000/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_60020000_EXISTS 1
#define DT_N_INST_3_espressif_esp32_timer DT_N_S_soc_S_counter_60020000
#define DT_N_NODELABEL_timer2             DT_N_S_soc_S_counter_60020000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_60020000_REG_NUM 1
#define DT_N_S_soc_S_counter_60020000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_REG_IDX_0_VAL_ADDRESS 1610743808 /* 0x60020000 */
#define DT_N_S_soc_S_counter_60020000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_counter_60020000_FOREACH_REG(fn) fn(DT_N_S_soc_S_counter_60020000, 0)
#define DT_N_S_soc_S_counter_60020000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, 0)
#define DT_N_S_soc_S_counter_60020000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_RANGES_NUM 0
#define DT_N_S_soc_S_counter_60020000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_60020000_IRQ_NUM 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_irq 53
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020000_IRQ_LEVEL 1
#define DT_N_S_soc_S_counter_60020000_COMPAT_MATCHES_espressif_esp32_timer 1
#define DT_N_S_soc_S_counter_60020000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_60020000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_COMPAT_MODEL_IDX_0 "esp32-timer"
#define DT_N_S_soc_S_counter_60020000_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_60020000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_60020000_P_group 1
#define DT_N_S_soc_S_counter_60020000_P_group_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020000_P_group_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_group_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_group_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_group_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_index 0
#define DT_N_S_soc_S_counter_60020000_P_index_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_counter_60020000_P_index_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_index_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_index_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_index_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_prescaler 2
#define DT_N_S_soc_S_counter_60020000_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_status "disabled"
#define DT_N_S_soc_S_counter_60020000_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_counter_60020000_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_counter_60020000_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_counter_60020000_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_counter_60020000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000, status, 0)
#define DT_N_S_soc_S_counter_60020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, status, 0)
#define DT_N_S_soc_S_counter_60020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_status_LEN 1
#define DT_N_S_soc_S_counter_60020000_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_compatible {"espressif,esp32-timer"}
#define DT_N_S_soc_S_counter_60020000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_compatible_IDX_0 "espressif,esp32-timer"
#define DT_N_S_soc_S_counter_60020000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-timer
#define DT_N_S_soc_S_counter_60020000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_timer
#define DT_N_S_soc_S_counter_60020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TIMER
#define DT_N_S_soc_S_counter_60020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000, compatible, 0)
#define DT_N_S_soc_S_counter_60020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, compatible, 0)
#define DT_N_S_soc_S_counter_60020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_60020000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_reg {1610743808 /* 0x60020000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_counter_60020000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_reg_IDX_0 1610743808
#define DT_N_S_soc_S_counter_60020000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_counter_60020000_P_reg_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupts {53 /* 0x35 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_0 53
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_counter_60020000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_counter_60020000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_VAL_offset 4
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_counter_60020000, clocks, 0, offset)
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, clocks, 0, offset)
#define DT_N_S_soc_S_counter_60020000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_counter_60020000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000, clocks, 0)
#define DT_N_S_soc_S_counter_60020000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000, clocks, 0)
#define DT_N_S_soc_S_counter_60020000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_P_clocks_LEN 1
#define DT_N_S_soc_S_counter_60020000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_60020000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_wakeup_source 0
#define DT_N_S_soc_S_counter_60020000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_60020000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@60020000/counter
 *
 * Node identifier: DT_N_S_soc_S_counter_60020000_S_counter
 *
 * Binding (compatible = espressif,esp32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_60020000_S_counter_PATH "/soc/counter@60020000/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_60020000_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_counter_60020000_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_counter_60020000_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_counter_60020000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/counter@60020000) identifier: */
#define DT_N_S_soc_S_counter_60020000_S_counter_PARENT DT_N_S_soc_S_counter_60020000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_60020000_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_60020000_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_counter_60020000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_60020000_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_counter_60020000_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_60020000_S_counter_HASH iUSZEEHrOjgouGvxolXes3pAkjQoylGsr7B78CVLa0Y

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_60020000_S_counter_ORD 77
#define DT_N_S_soc_S_counter_60020000_S_counter_ORD_STR_SORTABLE 00077

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_60020000_S_counter_REQUIRES_ORDS \
	76, /* /soc/counter@60020000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_60020000_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_60020000_S_counter_EXISTS 1
#define DT_N_INST_2_espressif_esp32_counter DT_N_S_soc_S_counter_60020000_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_60020000_S_counter_REG_NUM 0
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_60020000_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_counter_60020000_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_60020000_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_counter_60020000_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_counter_60020000_S_counter_COMPAT_MATCHES_espressif_esp32_counter 1
#define DT_N_S_soc_S_counter_60020000_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_60020000_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_COMPAT_MODEL_IDX_0 "esp32-counter"
#define DT_N_S_soc_S_counter_60020000_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_60020000_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status "disabled"
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000_S_counter, status, 0)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000_S_counter, status, 0)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible {"espressif,esp32-counter"}
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_IDX_0 "espressif,esp32-counter"
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-counter
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_counter
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_COUNTER
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020000_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020000_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020000_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_60020000_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_counter_60020000_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_60020000_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_60020000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@60020024
 *
 * Node identifier: DT_N_S_soc_S_counter_60020024
 *
 * Binding (compatible = espressif,esp32-timer):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-timer.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_60020024_PATH "/soc/counter@60020024"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_60020024_FULL_NAME "counter@60020024"
#define DT_N_S_soc_S_counter_60020024_FULL_NAME_UNQUOTED counter@60020024
#define DT_N_S_soc_S_counter_60020024_FULL_NAME_TOKEN counter_60020024
#define DT_N_S_soc_S_counter_60020024_FULL_NAME_UPPER_TOKEN COUNTER_60020024

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_counter_60020024_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_60020024_CHILD_IDX 36

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_60020024_NODELABEL_NUM 1
#define DT_N_S_soc_S_counter_60020024_FOREACH_NODELABEL(fn) fn(timer3)
#define DT_N_S_soc_S_counter_60020024_FOREACH_NODELABEL_VARGS(fn, ...) fn(timer3, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_60020024_CHILD_NUM 1
#define DT_N_S_soc_S_counter_60020024_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_counter_60020024_S_counter)
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024_S_counter)
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020024_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_60020024_HASH q7XUq8otw592MMX6Vq29YDJEwNtxuvJ4YXh2h6g4hwU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_60020024_ORD 78
#define DT_N_S_soc_S_counter_60020024_ORD_STR_SORTABLE 00078

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_60020024_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_60020024_SUPPORTS_ORDS \
	79, /* /soc/counter@60020024/counter */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_60020024_EXISTS 1
#define DT_N_INST_2_espressif_esp32_timer DT_N_S_soc_S_counter_60020024
#define DT_N_NODELABEL_timer3             DT_N_S_soc_S_counter_60020024

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_60020024_REG_NUM 1
#define DT_N_S_soc_S_counter_60020024_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_REG_IDX_0_VAL_ADDRESS 1610743844 /* 0x60020024 */
#define DT_N_S_soc_S_counter_60020024_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_counter_60020024_FOREACH_REG(fn) fn(DT_N_S_soc_S_counter_60020024, 0)
#define DT_N_S_soc_S_counter_60020024_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024, 0)
#define DT_N_S_soc_S_counter_60020024_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_RANGES_NUM 0
#define DT_N_S_soc_S_counter_60020024_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_60020024_IRQ_NUM 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_irq 54
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020024_IRQ_LEVEL 1
#define DT_N_S_soc_S_counter_60020024_COMPAT_MATCHES_espressif_esp32_timer 1
#define DT_N_S_soc_S_counter_60020024_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_60020024_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_COMPAT_MODEL_IDX_0 "esp32-timer"
#define DT_N_S_soc_S_counter_60020024_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_60020024_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_60020024_P_group 1
#define DT_N_S_soc_S_counter_60020024_P_group_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020024_P_group_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_group_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_group_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_group_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_index 1
#define DT_N_S_soc_S_counter_60020024_P_index_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020024_P_index_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_index_IDX_0_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_index_ENUM_VAL_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_index_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_prescaler 2
#define DT_N_S_soc_S_counter_60020024_P_prescaler_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_compatible {"espressif,esp32-timer"}
#define DT_N_S_soc_S_counter_60020024_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_compatible_IDX_0 "espressif,esp32-timer"
#define DT_N_S_soc_S_counter_60020024_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-timer
#define DT_N_S_soc_S_counter_60020024_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_timer
#define DT_N_S_soc_S_counter_60020024_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_TIMER
#define DT_N_S_soc_S_counter_60020024_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020024, compatible, 0)
#define DT_N_S_soc_S_counter_60020024_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024, compatible, 0)
#define DT_N_S_soc_S_counter_60020024_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_60020024_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_reg {1610743844 /* 0x60020024 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_counter_60020024_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_reg_IDX_0 1610743844
#define DT_N_S_soc_S_counter_60020024_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_reg_IDX_1 4096
#define DT_N_S_soc_S_counter_60020024_P_reg_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupts {54 /* 0x36 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_0 54
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_counter_60020024_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020024, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024, interrupt_parent, 0)
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_counter_60020024_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_VAL_offset 4
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_counter_60020024, clocks, 0, offset)
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024, clocks, 0, offset)
#define DT_N_S_soc_S_counter_60020024_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_counter_60020024_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020024, clocks, 0)
#define DT_N_S_soc_S_counter_60020024_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024, clocks, 0)
#define DT_N_S_soc_S_counter_60020024_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_P_clocks_LEN 1
#define DT_N_S_soc_S_counter_60020024_P_clocks_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_60020024_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_wakeup_source 0
#define DT_N_S_soc_S_counter_60020024_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_60020024_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/counter@60020024/counter
 *
 * Node identifier: DT_N_S_soc_S_counter_60020024_S_counter
 *
 * Binding (compatible = espressif,esp32-counter):
 *   $ZEPHYR_BASE/dts/bindings/counter/espressif,esp32-counter.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_counter_60020024_S_counter_PATH "/soc/counter@60020024/counter"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_counter_60020024_S_counter_FULL_NAME "counter"
#define DT_N_S_soc_S_counter_60020024_S_counter_FULL_NAME_UNQUOTED counter
#define DT_N_S_soc_S_counter_60020024_S_counter_FULL_NAME_TOKEN counter
#define DT_N_S_soc_S_counter_60020024_S_counter_FULL_NAME_UPPER_TOKEN COUNTER

/* Node parent (/soc/counter@60020024) identifier: */
#define DT_N_S_soc_S_counter_60020024_S_counter_PARENT DT_N_S_soc_S_counter_60020024

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_counter_60020024_S_counter_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_counter_60020024_S_counter_NODELABEL_NUM 0
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_counter_60020024) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_counter_60020024_S_counter_CHILD_NUM 0
#define DT_N_S_soc_S_counter_60020024_S_counter_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_counter_60020024_S_counter_HASH wmieNtyjn9sQES1VH5SAPFutSItagKibxS7ndwgbUKY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_counter_60020024_S_counter_ORD 79
#define DT_N_S_soc_S_counter_60020024_S_counter_ORD_STR_SORTABLE 00079

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_counter_60020024_S_counter_REQUIRES_ORDS \
	78, /* /soc/counter@60020024 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_counter_60020024_S_counter_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_counter_60020024_S_counter_EXISTS 1
#define DT_N_INST_3_espressif_esp32_counter DT_N_S_soc_S_counter_60020024_S_counter

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_counter_60020024_S_counter_REG_NUM 0
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_REG(fn) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_counter_60020024_S_counter_RANGES_NUM 0
#define DT_N_S_soc_S_counter_60020024_S_counter_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_counter_60020024_S_counter_IRQ_NUM 0
#define DT_N_S_soc_S_counter_60020024_S_counter_IRQ_LEVEL 0
#define DT_N_S_soc_S_counter_60020024_S_counter_COMPAT_MATCHES_espressif_esp32_counter 1
#define DT_N_S_soc_S_counter_60020024_S_counter_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_counter_60020024_S_counter_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_COMPAT_MODEL_IDX_0 "esp32-counter"
#define DT_N_S_soc_S_counter_60020024_S_counter_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_counter_60020024_S_counter_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status "disabled"
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020024_S_counter, status, 0)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024_S_counter, status, 0)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_LEN 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_status_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible {"espressif,esp32-counter"}
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_IDX_0 "espressif,esp32-counter"
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-counter
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_counter
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_COUNTER
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_counter_60020024_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_counter_60020024_S_counter, compatible, 0)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_counter_60020024_S_counter, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_LEN 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_compatible_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_counter_60020024_S_counter_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_wakeup_source 0
#define DT_N_S_soc_S_counter_60020024_S_counter_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_counter_60020024_S_counter_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_counter_60020024_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000
 *
 * Binding (compatible = espressif,esp32-flash-controller):
 *   $ZEPHYR_BASE/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_PATH "/soc/flash-controller@60002000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_FULL_NAME "flash-controller@60002000"
#define DT_N_S_soc_S_flash_controller_60002000_FULL_NAME_UNQUOTED flash-controller@60002000
#define DT_N_S_soc_S_flash_controller_60002000_FULL_NAME_TOKEN flash_controller_60002000
#define DT_N_S_soc_S_flash_controller_60002000_FULL_NAME_UPPER_TOKEN FLASH_CONTROLLER_60002000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_CHILD_IDX 14

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_NODELABEL(fn) fn(flash)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_60002000_CHILD_UNIT_ADDR_INT_0 DT_N_S_soc_S_flash_controller_60002000_S_flash_0
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_HASH yd4D2IggpKw4LyE398Naff07xJbYibUkiq_qk5dUqD8

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_ORD 80
#define DT_N_S_soc_S_flash_controller_60002000_ORD_STR_SORTABLE 00080

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_SUPPORTS_ORDS \
	81, /* /soc/flash-controller@60002000/flash@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_flash_controller DT_N_S_soc_S_flash_controller_60002000
#define DT_N_NODELABEL_flash                         DT_N_S_soc_S_flash_controller_60002000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_REG_IDX_0_VAL_ADDRESS 1610620928 /* 0x60002000 */
#define DT_N_S_soc_S_flash_controller_60002000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_COMPAT_MATCHES_espressif_esp32_flash_controller 1
#define DT_N_S_soc_S_flash_controller_60002000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_flash_controller_60002000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_COMPAT_MODEL_IDX_0 "esp32-flash-controller"
#define DT_N_S_soc_S_flash_controller_60002000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_P_reg {1610620928 /* 0x60002000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_flash_controller_60002000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_reg_IDX_0 1610620928
#define DT_N_S_soc_S_flash_controller_60002000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_flash_controller_60002000_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible {"espressif,esp32-flash-controller"}
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_IDX_0 "espressif,esp32-flash-controller"
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-flash-controller
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_flash_controller
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_FLASH_CONTROLLER
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_60002000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_60002000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_60002000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0
 *
 * Binding (compatible = soc-nv-flash):
 *   $ZEPHYR_BASE/dts/bindings/mtd/soc-nv-flash.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_PATH "/soc/flash-controller@60002000/flash@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FULL_NAME "flash@0"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FULL_NAME_UNQUOTED flash@0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FULL_NAME_TOKEN flash_0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FULL_NAME_UPPER_TOKEN FLASH_0

/* Node parent (/soc/flash-controller@60002000) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_PARENT DT_N_S_soc_S_flash_controller_60002000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_NODELABEL(fn) fn(flash0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(flash0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_CHILD_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_HASH D2mNQTsAafBKTZogWP5ZJcwnGR7dkZH4NbPP40TPifI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_ORD 81
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_ORD_STR_SORTABLE 00081

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_REQUIRES_ORDS \
	80, /* /soc/flash-controller@60002000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_SUPPORTS_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_EXISTS 1
#define DT_N_INST_0_soc_nv_flash DT_N_S_soc_S_flash_controller_60002000_S_flash_0
#define DT_N_NODELABEL_flash0    DT_N_S_soc_S_flash_controller_60002000_S_flash_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_REG_IDX_0_VAL_SIZE 8388608 /* 0x800000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_COMPAT_MATCHES_soc_nv_flash 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_erase_block_size 4096
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_erase_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_write_block_size 4
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_write_block_size_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible {"soc-nv-flash"}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_IDX_0 "soc-nv-flash"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_IDX_0_STRING_UNQUOTED soc-nv-flash
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_IDX_0_STRING_TOKEN soc_nv_flash
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SOC_NV_FLASH
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg {0 /* 0x0 */, 8388608 /* 0x800000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg_IDX_1 8388608
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions
 *
 * Binding (compatible = fixed-partitions):
 *   $ZEPHYR_BASE/dts/bindings/mtd/fixed-partitions.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_PATH "/soc/flash-controller@60002000/flash@0/partitions"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FULL_NAME "partitions"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FULL_NAME_UNQUOTED partitions
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FULL_NAME_TOKEN partitions
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS

/* Node parent (/soc/flash-controller@60002000/flash@0) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_NODELABEL_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_NODELABEL(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_NODELABEL_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_NUM 11
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_NUM_STATUS_OKAY 11
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_0 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_65536 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_131072 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_1507328 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_2883584 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_3342336 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_3801088 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_3833856 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_3866624 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_4063232 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_CHILD_UNIT_ADDR_INT_4190208 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_HASH dNzhNxyK81xeQFYip2CZ9rCb0VdF2BCsUgOYjZqcpMo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_ORD 82
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_ORD_STR_SORTABLE 00082

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_REQUIRES_ORDS \
	81, /* /soc/flash-controller@60002000/flash@0 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_SUPPORTS_ORDS \
	83, /* /soc/flash-controller@60002000/flash@0/partitions/partition@0 */ \
	84, /* /soc/flash-controller@60002000/flash@0/partitions/partition@10000 */ \
	85, /* /soc/flash-controller@60002000/flash@0/partitions/partition@20000 */ \
	86, /* /soc/flash-controller@60002000/flash@0/partitions/partition@170000 */ \
	87, /* /soc/flash-controller@60002000/flash@0/partitions/partition@2c0000 */ \
	88, /* /soc/flash-controller@60002000/flash@0/partitions/partition@330000 */ \
	89, /* /soc/flash-controller@60002000/flash@0/partitions/partition@3a0000 */ \
	90, /* /soc/flash-controller@60002000/flash@0/partitions/partition@3a8000 */ \
	91, /* /soc/flash-controller@60002000/flash@0/partitions/partition@3b0000 */ \
	92, /* /soc/flash-controller@60002000/flash@0/partitions/partition@3e0000 */ \
	93, /* /soc/flash-controller@60002000/flash@0/partitions/partition@3ff000 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_EXISTS 1
#define DT_N_INST_0_fixed_partitions DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_REG_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_REG(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible {"fixed-partitions"}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_IDX_0 "fixed-partitions"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_IDX_0_STRING_UNQUOTED fixed-partitions
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_IDX_0_STRING_TOKEN fixed_partitions
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_PARTITIONS
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, compatible, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_compatible_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_wakeup_source 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@0
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FULL_NAME "partition@0"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL(fn) fn(boot_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(boot_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_HASH oDsImwagDdfCPnWV2WOVcSz6DvQuTknj1gY7ra4w5Cw

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_ORD 83
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_ORD_STR_SORTABLE 00083

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_EXISTS 1
#define DT_N_NODELABEL_boot_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID 0

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label "mcuboot"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UNQUOTED mcuboot
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN mcuboot
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN MCUBOOT
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0 "mcuboot"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1 65536
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@10000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@10000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME "partition@10000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_UNQUOTED partition@10000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_TOKEN partition_10000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME_UPPER_TOKEN PARTITION_10000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL(fn) fn(sys_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sys_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_HASH fieo_ZZ_e2gacspwZIAewOHWM7IxeT3uY7EGlWW2yes

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_ORD 84
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_ORD_STR_SORTABLE 00084

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_EXISTS 1
#define DT_N_NODELABEL_sys_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS 65536 /* 0x10000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID 1

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label "sys"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UNQUOTED sys
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN sys
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN SYS
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0 "sys"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg {65536 /* 0x10000 */, 65536 /* 0x10000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0 65536
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1 65536
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@20000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@20000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FULL_NAME "partition@20000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FULL_NAME_UNQUOTED partition@20000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FULL_NAME_TOKEN partition_20000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FULL_NAME_UPPER_TOKEN PARTITION_20000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_CHILD_IDX 2

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_NODELABEL(fn) fn(slot0_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_HASH _RYkLIzjY4UgPmWibu0PcD8f_q1lghSkV21XtY_S_TM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_ORD 85
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_ORD_STR_SORTABLE 00085

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_EXISTS 1
#define DT_N_NODELABEL_slot0_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_REG_IDX_0_VAL_ADDRESS 131072 /* 0x20000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_REG_IDX_0_VAL_SIZE 1376256 /* 0x150000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_PARTITION_ID 2

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label "image-0"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_STRING_UNQUOTED image-0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_STRING_TOKEN image_0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_STRING_UPPER_TOKEN IMAGE_0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_IDX_0 "image-0"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg {131072 /* 0x20000 */, 1376256 /* 0x150000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg_IDX_0 131072
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg_IDX_1 1376256
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@170000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@170000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FULL_NAME "partition@170000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FULL_NAME_UNQUOTED partition@170000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FULL_NAME_TOKEN partition_170000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FULL_NAME_UPPER_TOKEN PARTITION_170000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_CHILD_IDX 3

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_NODELABEL(fn) fn(slot1_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_HASH _VUyUmkd_u2hu0MU_IKV1_jAVg0T_PtFaII_lPXtG3Q

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_ORD 86
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_ORD_STR_SORTABLE 00086

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_EXISTS 1
#define DT_N_NODELABEL_slot1_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_REG_IDX_0_VAL_ADDRESS 1507328 /* 0x170000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_REG_IDX_0_VAL_SIZE 1376256 /* 0x150000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_PARTITION_ID 3

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label "image-1"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_STRING_UNQUOTED image-1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_STRING_TOKEN image_1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_STRING_UPPER_TOKEN IMAGE_1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_IDX_0 "image-1"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg {1507328 /* 0x170000 */, 1376256 /* 0x150000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg_IDX_0 1507328
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg_IDX_1 1376256
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@2c0000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@2c0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FULL_NAME "partition@2c0000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FULL_NAME_UNQUOTED partition@2c0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FULL_NAME_TOKEN partition_2c0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FULL_NAME_UPPER_TOKEN PARTITION_2C0000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_CHILD_IDX 4

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_NODELABEL(fn) fn(slot0_appcpu_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_appcpu_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_HASH mgJTA6mdjCUIKu0BM_g6Crq3a6L7JZLHyJTgl1I_egE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_ORD 87
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_ORD_STR_SORTABLE 00087

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_EXISTS 1
#define DT_N_NODELABEL_slot0_appcpu_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_REG_IDX_0_VAL_ADDRESS 2883584 /* 0x2c0000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_PARTITION_ID 4

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label "image-0-appcpu"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_STRING_UNQUOTED image-0-appcpu
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_STRING_TOKEN image_0_appcpu
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_STRING_UPPER_TOKEN IMAGE_0_APPCPU
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_IDX_0 "image-0-appcpu"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg {2883584 /* 0x2c0000 */, 458752 /* 0x70000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg_IDX_0 2883584
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg_IDX_1 458752
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@330000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@330000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FULL_NAME "partition@330000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FULL_NAME_UNQUOTED partition@330000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FULL_NAME_TOKEN partition_330000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FULL_NAME_UPPER_TOKEN PARTITION_330000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_CHILD_IDX 5

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_NODELABEL(fn) fn(slot1_appcpu_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_appcpu_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_HASH x7dGVvVNfxVTT9coyYV5eMB7_C4THzsLcHou93SEXIQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_ORD 88
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_ORD_STR_SORTABLE 00088

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_EXISTS 1
#define DT_N_NODELABEL_slot1_appcpu_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_REG_IDX_0_VAL_ADDRESS 3342336 /* 0x330000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_REG_IDX_0_VAL_SIZE 458752 /* 0x70000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_PARTITION_ID 5

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label "image-1-appcpu"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_STRING_UNQUOTED image-1-appcpu
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_STRING_TOKEN image_1_appcpu
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_STRING_UPPER_TOKEN IMAGE_1_APPCPU
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_IDX_0 "image-1-appcpu"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg {3342336 /* 0x330000 */, 458752 /* 0x70000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg_IDX_0 3342336
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg_IDX_1 458752
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@3a0000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@3a0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FULL_NAME "partition@3a0000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FULL_NAME_UNQUOTED partition@3a0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FULL_NAME_TOKEN partition_3a0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FULL_NAME_UPPER_TOKEN PARTITION_3A0000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_CHILD_IDX 6

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_NODELABEL(fn) fn(slot0_lpcore_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot0_lpcore_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_HASH MFbK2mwgeWhCZwHgtDHUw3nXa2bjAnxM3Em9ay4u2KY

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_ORD 89
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_ORD_STR_SORTABLE 00089

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_EXISTS 1
#define DT_N_NODELABEL_slot0_lpcore_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_REG_IDX_0_VAL_ADDRESS 3801088 /* 0x3a0000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_PARTITION_ID 6

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label "image-0-lpcore"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_STRING_UNQUOTED image-0-lpcore
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_STRING_TOKEN image_0_lpcore
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_STRING_UPPER_TOKEN IMAGE_0_LPCORE
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_IDX_0 "image-0-lpcore"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg {3801088 /* 0x3a0000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg_IDX_0 3801088
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@3a8000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@3a8000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FULL_NAME "partition@3a8000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FULL_NAME_UNQUOTED partition@3a8000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FULL_NAME_TOKEN partition_3a8000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FULL_NAME_UPPER_TOKEN PARTITION_3A8000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_CHILD_IDX 7

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_NODELABEL(fn) fn(slot1_lpcore_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_NODELABEL_VARGS(fn, ...) fn(slot1_lpcore_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_HASH H_pMNiTzPzv5CHmjNphsrycI6__KzwyiYJbytejQtTs

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_ORD 90
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_ORD_STR_SORTABLE 00090

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_EXISTS 1
#define DT_N_NODELABEL_slot1_lpcore_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_REG_IDX_0_VAL_ADDRESS 3833856 /* 0x3a8000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_PARTITION_ID 7

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label "image-1-lpcore"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_STRING_UNQUOTED image-1-lpcore
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_STRING_TOKEN image_1_lpcore
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_STRING_UPPER_TOKEN IMAGE_1_LPCORE
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_IDX_0 "image-1-lpcore"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg {3833856 /* 0x3a8000 */, 32768 /* 0x8000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg_IDX_0 3833856
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg_IDX_1 32768
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@3b0000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@3b0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FULL_NAME "partition@3b0000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FULL_NAME_UNQUOTED partition@3b0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FULL_NAME_TOKEN partition_3b0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FULL_NAME_UPPER_TOKEN PARTITION_3B0000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_CHILD_IDX 8

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_NODELABEL(fn) fn(storage_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(storage_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_HASH FwNzLzGEzQBAe3N4r3VO2x4UwK4rCMBOfdTATEQvVjM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_ORD 91
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_ORD_STR_SORTABLE 00091

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_EXISTS 1
#define DT_N_NODELABEL_storage_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_REG_IDX_0_VAL_ADDRESS 3866624 /* 0x3b0000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_REG_IDX_0_VAL_SIZE 196608 /* 0x30000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_PARTITION_ID 8

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label "storage"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_STRING_UNQUOTED storage
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_STRING_TOKEN storage
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_STRING_UPPER_TOKEN STORAGE
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_IDX_0 "storage"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg {3866624 /* 0x3b0000 */, 196608 /* 0x30000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg_IDX_0 3866624
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg_IDX_1 196608
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@3e0000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@3e0000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FULL_NAME "partition@3e0000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FULL_NAME_UNQUOTED partition@3e0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FULL_NAME_TOKEN partition_3e0000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FULL_NAME_UPPER_TOKEN PARTITION_3E0000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_CHILD_IDX 9

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_NODELABEL(fn) fn(scratch_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_NODELABEL_VARGS(fn, ...) fn(scratch_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_HASH x1ZlLZHhfqkhNm59vRztuqo3qPs7ruj_uO7YXxbgDRI

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_ORD 92
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_ORD_STR_SORTABLE 00092

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_EXISTS 1
#define DT_N_NODELABEL_scratch_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_REG_IDX_0_VAL_ADDRESS 4063232 /* 0x3e0000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_REG_IDX_0_VAL_SIZE 126976 /* 0x1f000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_PARTITION_ID 9

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label "image-scratch"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_STRING_UNQUOTED image-scratch
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_STRING_TOKEN image_scratch
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_STRING_UPPER_TOKEN IMAGE_SCRATCH
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_IDX_0 "image-scratch"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg {4063232 /* 0x3e0000 */, 126976 /* 0x1f000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg_IDX_0 4063232
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg_IDX_1 126976
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/flash-controller@60002000/flash@0/partitions/partition@3ff000
 *
 * Node identifier: DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_PATH "/soc/flash-controller@60002000/flash@0/partitions/partition@3ff000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FULL_NAME "partition@3ff000"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FULL_NAME_UNQUOTED partition@3ff000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FULL_NAME_TOKEN partition_3ff000
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FULL_NAME_UPPER_TOKEN PARTITION_3FF000

/* Node parent (/soc/flash-controller@60002000/flash@0/partitions) identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_PARENT DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_CHILD_IDX 10

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_NODELABEL_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_NODELABEL(fn) fn(coredump_partition)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_NODELABEL_VARGS(fn, ...) fn(coredump_partition, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_CHILD_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_HASH 2bpF1B_hYyCbTR1o1QejsFP72ANPsszTta3EJTOEFFU

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_ORD 93
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_ORD_STR_SORTABLE 00093

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_REQUIRES_ORDS \
	82, /* /soc/flash-controller@60002000/flash@0/partitions */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_EXISTS 1
#define DT_N_NODELABEL_coredump_partition DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_REG_NUM 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_REG_IDX_0_VAL_ADDRESS 4190208 /* 0x3ff000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_REG(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_RANGES_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_IRQ_NUM 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_IRQ_LEVEL 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_PINCTRL_NUM 0

/* fixed-partitions identifier: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_PARTITION_ID 10

/* Generic property macros: */
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label "coredump"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_STRING_UNQUOTED coredump
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_STRING_TOKEN coredump
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_STRING_UPPER_TOKEN COREDUMP
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_IDX_0 "coredump"
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, label, 0)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, label, 0, __VA_ARGS__)
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_LEN 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_label_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_read_only 0
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_read_only_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg {4190208 /* 0x3ff000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg_IDX_0 4190208
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000_P_reg_EXISTS 1

/*
 * Devicetree node: /soc/gpio/gpio@60004800
 *
 * Node identifier: DT_N_S_soc_S_gpio_S_gpio_60004800
 *
 * Binding (compatible = espressif,esp32-gpio):
 *   $ZEPHYR_BASE/dts/bindings/gpio/espressif,esp32-gpio.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_PATH "/soc/gpio/gpio@60004800"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FULL_NAME "gpio@60004800"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FULL_NAME_UNQUOTED gpio@60004800
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FULL_NAME_TOKEN gpio_60004800
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FULL_NAME_UPPER_TOKEN GPIO_60004800

/* Node parent (/soc/gpio) identifier: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_PARENT DT_N_S_soc_S_gpio

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_NODELABEL_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_NODELABEL(fn) fn(gpio1)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_NODELABEL_VARGS(fn, ...) fn(gpio1, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_CHILD_NUM 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_HASH tkds8hEbm4oeIpnghhwVoKJPakkp8n6NOFephgEpHvo

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_ORD 94
#define DT_N_S_soc_S_gpio_S_gpio_60004800_ORD_STR_SORTABLE 00094

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_REQUIRES_ORDS \
	13, /* /soc/gpio */ \
	14, /* /soc/interrupt-controller@600c2000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_EXISTS 1
#define DT_N_INST_1_espressif_esp32_gpio DT_N_S_soc_S_gpio_S_gpio_60004800
#define DT_N_NODELABEL_gpio1             DT_N_S_soc_S_gpio_S_gpio_60004800

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_REG_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_REG_IDX_0_VAL_ADDRESS 1610631168 /* 0x60004800 */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_REG_IDX_0_VAL_SIZE 2048 /* 0x800 */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_REG(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_RANGES_NUM 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_NUM 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_irq 16
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004800_IRQ_LEVEL 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_COMPAT_MATCHES_espressif_esp32_gpio 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_COMPAT_MODEL_IDX_0 "esp32-gpio"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg {1610631168 /* 0x60004800 */, 2048 /* 0x800 */}
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg_IDX_0 1610631168
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg_IDX_1 2048
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_reg_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_gpio_controller 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_gpio_controller_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_ngpios 22
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_ngpios_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status "okay"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, status, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, status, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_status_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible {"espressif,esp32-gpio"}
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_IDX_0 "espressif,esp32-gpio"
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-gpio
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_gpio
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_GPIO
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, compatible, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, compatible, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_compatible_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts {16 /* 0x10 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_0 16
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, interrupt_parent, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, interrupt_parent, 0)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_wakeup_source 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_gpio_S_gpio_60004800_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/lcd_cam@60041000
 *
 * Node identifier: DT_N_S_soc_S_lcd_cam_60041000
 *
 * Binding (compatible = espressif,esp32-lcd-cam):
 *   $ZEPHYR_BASE/dts/bindings/misc/espressif,esp32-lcd-cam.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_lcd_cam_60041000_PATH "/soc/lcd_cam@60041000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_lcd_cam_60041000_FULL_NAME "lcd_cam@60041000"
#define DT_N_S_soc_S_lcd_cam_60041000_FULL_NAME_UNQUOTED lcd_cam@60041000
#define DT_N_S_soc_S_lcd_cam_60041000_FULL_NAME_TOKEN lcd_cam_60041000
#define DT_N_S_soc_S_lcd_cam_60041000_FULL_NAME_UPPER_TOKEN LCD_CAM_60041000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_lcd_cam_60041000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_lcd_cam_60041000_CHILD_IDX 30

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_lcd_cam_60041000_NODELABEL_NUM 1
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_NODELABEL(fn) fn(lcd_cam)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_NODELABEL_VARGS(fn, ...) fn(lcd_cam, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_lcd_cam_60041000_CHILD_NUM 2
#define DT_N_S_soc_S_lcd_cam_60041000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_lcd_cam_60041000_HASH xfgRleDgbzEuPVZEMcIidCarjrzyGwvfZGB4rFHc0E4

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_lcd_cam_60041000_ORD 95
#define DT_N_S_soc_S_lcd_cam_60041000_ORD_STR_SORTABLE 00095

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_lcd_cam_60041000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */ \
	42, /* /soc/dma@6003f000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_lcd_cam_60041000_SUPPORTS_ORDS \
	96, /* /soc/lcd_cam@60041000/lcd_cam_disp */ \
	97, /* /soc/lcd_cam@60041000/lcd_cam_dvp */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_lcd_cam_60041000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_lcd_cam DT_N_S_soc_S_lcd_cam_60041000
#define DT_N_NODELABEL_lcd_cam              DT_N_S_soc_S_lcd_cam_60041000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_lcd_cam_60041000_REG_NUM 1
#define DT_N_S_soc_S_lcd_cam_60041000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_REG_IDX_0_VAL_ADDRESS 1610878976 /* 0x60041000 */
#define DT_N_S_soc_S_lcd_cam_60041000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_REG(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_RANGES_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_NUM 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_irq 24
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_lcd_cam_60041000_IRQ_LEVEL 1
#define DT_N_S_soc_S_lcd_cam_60041000_COMPAT_MATCHES_espressif_esp32_lcd_cam 1
#define DT_N_S_soc_S_lcd_cam_60041000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_lcd_cam_60041000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_COMPAT_MODEL_IDX_0 "esp32-lcd-cam"
#define DT_N_S_soc_S_lcd_cam_60041000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_lcd_cam_60041000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible {"espressif,esp32-lcd-cam"}
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_IDX_0 "espressif,esp32-lcd-cam"
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-lcd-cam
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_lcd_cam
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_LCD_CAM
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, compatible, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, compatible, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_LEN 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg {1610878976 /* 0x60041000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg_IDX_0 1610878976
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_lcd_cam_60041000_P_reg_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_0 24
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, interrupt_parent, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, interrupt_parent, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_VAL_offset 2
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0, offset)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0, offset)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_LEN 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_VAL_channel 6
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_NAME "rx"
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_IDX 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, rx, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, rx, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_NUM_CELLS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_VAL_channel DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_0_VAL_channel
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_rx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_VAL_channel 7
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_FOREACH_CELL(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_NUM_CELLS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_NAME "tx"
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_IDX 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_FOREACH_CELL(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, tx, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, tx, channel)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_NUM_CELLS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_PH DT_N_S_soc_S_dma_6003f000
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_VAL_channel DT_N_S_soc_S_lcd_cam_60041000_P_dmas_IDX_1_VAL_channel
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_NAME_tx_VAL_channel_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0) \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dmas, 1, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_LEN 2
#define DT_N_S_soc_S_lcd_cam_60041000_P_dmas_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names {"rx", "tx"}
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_0 "rx"
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_0_STRING_UNQUOTED rx
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_0_STRING_TOKEN rx
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_0_STRING_UPPER_TOKEN RX
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_1_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_1 "tx"
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_1_STRING_UNQUOTED tx
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_1_STRING_TOKEN tx
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_IDX_1_STRING_UPPER_TOKEN TX
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 0) \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 1)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 0) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 1)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 0, __VA_ARGS__) \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_lcd_cam_60041000, dma_names, 1, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_LEN 2
#define DT_N_S_soc_S_lcd_cam_60041000_P_dma_names_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_wakeup_source 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_lcd_cam_60041000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/lcd_cam@60041000/lcd_cam_disp
 *
 * Node identifier: DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp
 *
 * Binding (compatible = espressif,esp32-lcd-cam-mipi-dbi):
 *   $ZEPHYR_BASE/dts/bindings/mipi-dbi/espressif,esp32-lcd-cam-mipi-dbi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_PATH "/soc/lcd_cam@60041000/lcd_cam_disp"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FULL_NAME "lcd_cam_disp"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FULL_NAME_UNQUOTED lcd_cam_disp
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FULL_NAME_TOKEN lcd_cam_disp
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FULL_NAME_UPPER_TOKEN LCD_CAM_DISP

/* Node parent (/soc/lcd_cam@60041000) identifier: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_PARENT DT_N_S_soc_S_lcd_cam_60041000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_NODELABEL_NUM 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_NODELABEL(fn) fn(lcd_cam_disp)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_NODELABEL_VARGS(fn, ...) fn(lcd_cam_disp, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_CHILD_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_HASH FA6kZQBIwJ48c14hSuUIt8V8fwVUiZAmxv2sQ5C0P7s

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_ORD 96
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_ORD_STR_SORTABLE 00096

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_REQUIRES_ORDS \
	95, /* /soc/lcd_cam@60041000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_EXISTS 1
#define DT_N_INST_0_espressif_esp32_lcd_cam_mipi_dbi DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp
#define DT_N_NODELABEL_lcd_cam_disp                  DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_REG_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_REG(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_RANGES_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_IRQ_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_IRQ_LEVEL 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_COMPAT_MATCHES_espressif_esp32_lcd_cam_mipi_dbi 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_COMPAT_MODEL_IDX_0 "esp32-lcd-cam-mipi-dbi"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status "disabled"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, status, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, status, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_LEN 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_status_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible {"espressif,esp32-lcd-cam-mipi-dbi"}
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_IDX_0 "espressif,esp32-lcd-cam-mipi-dbi"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-lcd-cam-mipi-dbi
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_lcd_cam_mipi_dbi
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_LCD_CAM_MIPI_DBI
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, compatible, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, compatible, 0)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_LEN 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_compatible_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_wakeup_source 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/lcd_cam@60041000/lcd_cam_dvp
 *
 * Node identifier: DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp
 *
 * Binding (compatible = espressif,esp32-lcd-cam-dvp):
 *   $ZEPHYR_BASE/dts/bindings/video/espressif,esp32-lcd-cam-dvp.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_PATH "/soc/lcd_cam@60041000/lcd_cam_dvp"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FULL_NAME "lcd_cam_dvp"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FULL_NAME_UNQUOTED lcd_cam_dvp
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FULL_NAME_TOKEN lcd_cam_dvp
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FULL_NAME_UPPER_TOKEN LCD_CAM_DVP

/* Node parent (/soc/lcd_cam@60041000) identifier: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_PARENT DT_N_S_soc_S_lcd_cam_60041000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_NODELABEL_NUM 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_NODELABEL(fn) fn(lcd_cam_dvp)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_NODELABEL_VARGS(fn, ...) fn(lcd_cam_dvp, __VA_ARGS__)
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_CHILD_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_HASH c101Gy_c3FK_chPw75ej7q85cTtSUu4pqKpwTOsHZPM

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_ORD 97
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_ORD_STR_SORTABLE 00097

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_REQUIRES_ORDS \
	95, /* /soc/lcd_cam@60041000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_EXISTS 1
#define DT_N_INST_0_espressif_esp32_lcd_cam_dvp DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp
#define DT_N_NODELABEL_lcd_cam_dvp              DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_REG_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_REG(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_RANGES_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_IRQ_NUM 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_IRQ_LEVEL 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_COMPAT_MATCHES_espressif_esp32_lcd_cam_dvp 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_COMPAT_MODEL_IDX_0 "esp32-lcd-cam-dvp"
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_byte_order 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_byte_order_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_bit_order 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_bit_order_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_pclk 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_pclk_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_de 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_de_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_hsync 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_hsync_EXISTS 1
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_vsync 0
#define DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp_P_invert_vsync_EXISTS 1

/*
 * Devicetree node: /soc/memory@3c000000
 *
 * Node identifier: DT_N_S_soc_S_memory_3c000000
 *
 * Binding (compatible = zephyr,memory-region):
 *   $ZEPHYR_BASE/dts/bindings/base/zephyr,memory-region.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3c000000_PATH "/soc/memory@3c000000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3c000000_FULL_NAME "memory@3c000000"
#define DT_N_S_soc_S_memory_3c000000_FULL_NAME_UNQUOTED memory@3c000000
#define DT_N_S_soc_S_memory_3c000000_FULL_NAME_TOKEN memory_3c000000
#define DT_N_S_soc_S_memory_3c000000_FULL_NAME_UPPER_TOKEN MEMORY_3C000000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_memory_3c000000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3c000000_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3c000000_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3c000000_FOREACH_NODELABEL(fn) fn(dcache0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_NODELABEL_VARGS(fn, ...) fn(dcache0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3c000000_CHILD_NUM 1
#define DT_N_S_soc_S_memory_3c000000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_memory_3c000000_S_psram0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000_S_psram0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_memory_3c000000_S_psram0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000_S_psram0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_memory_3c000000_HASH jrd5_8sYqBEpYXXIJHTi5X75qQEPgADmOuXc2NGPHNQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3c000000_ORD 98
#define DT_N_S_soc_S_memory_3c000000_ORD_STR_SORTABLE 00098

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3c000000_REQUIRES_ORDS \
	12, /* /soc */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3c000000_SUPPORTS_ORDS \
	99, /* /soc/memory@3c000000/psram0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3c000000_EXISTS 1
#define DT_N_INST_1_zephyr_memory_region DT_N_S_soc_S_memory_3c000000
#define DT_N_NODELABEL_dcache0           DT_N_S_soc_S_memory_3c000000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3c000000_REG_NUM 1
#define DT_N_S_soc_S_memory_3c000000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_REG_IDX_0_VAL_ADDRESS 1006632960 /* 0x3c000000 */
#define DT_N_S_soc_S_memory_3c000000_REG_IDX_0_VAL_SIZE 33554432 /* 0x2000000 */
#define DT_N_S_soc_S_memory_3c000000_FOREACH_REG(fn) fn(DT_N_S_soc_S_memory_3c000000, 0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000, 0)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3c000000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3c000000_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3c000000_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3c000000_COMPAT_MATCHES_zephyr_memory_region 1
#define DT_N_S_soc_S_memory_3c000000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_COMPAT_VENDOR_IDX_0 "Zephyr Project"
#define DT_N_S_soc_S_memory_3c000000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_COMPAT_MODEL_IDX_0 "memory-region"
#define DT_N_S_soc_S_memory_3c000000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3c000000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region "DCACHE0"
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_STRING_UNQUOTED DCACHE0
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_STRING_TOKEN DCACHE0
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_STRING_UPPER_TOKEN DCACHE0
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_IDX_0 "DCACHE0"
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3c000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000, zephyr_memory_region, 0)
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000, zephyr_memory_region, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_LEN 1
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_memory_region_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_compatible {"zephyr,memory-region"}
#define DT_N_S_soc_S_memory_3c000000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_compatible_IDX_0 "zephyr,memory-region"
#define DT_N_S_soc_S_memory_3c000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region
#define DT_N_S_soc_S_memory_3c000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region
#define DT_N_S_soc_S_memory_3c000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION
#define DT_N_S_soc_S_memory_3c000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3c000000, compatible, 0)
#define DT_N_S_soc_S_memory_3c000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000, compatible, 0)
#define DT_N_S_soc_S_memory_3c000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_3c000000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_reg {1006632960 /* 0x3c000000 */, 33554432 /* 0x2000000 */}
#define DT_N_S_soc_S_memory_3c000000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_reg_IDX_0 1006632960
#define DT_N_S_soc_S_memory_3c000000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_reg_IDX_1 33554432
#define DT_N_S_soc_S_memory_3c000000_P_reg_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3c000000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3c000000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/memory@3c000000/psram0
 *
 * Node identifier: DT_N_S_soc_S_memory_3c000000_S_psram0
 *
 * Binding (compatible = espressif,esp32-psram):
 *   $ZEPHYR_BASE/dts/bindings/memory-controllers/espressif,esp32-psram.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_PATH "/soc/memory@3c000000/psram0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FULL_NAME "psram0"
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FULL_NAME_UNQUOTED psram0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FULL_NAME_TOKEN psram0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FULL_NAME_UPPER_TOKEN PSRAM0

/* Node parent (/soc/memory@3c000000) identifier: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_PARENT DT_N_S_soc_S_memory_3c000000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_NODELABEL_NUM 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_NODELABEL(fn) fn(psram0)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_NODELABEL_VARGS(fn, ...) fn(psram0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_CHILD_NUM 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_HASH Mf0fUfdBFggNOZ4s_rnJO9oqoFNzpvQPdJXAViY8TDc

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_ORD 99
#define DT_N_S_soc_S_memory_3c000000_S_psram0_ORD_STR_SORTABLE 00099

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_REQUIRES_ORDS \
	98, /* /soc/memory@3c000000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_EXISTS 1
#define DT_N_INST_0_espressif_esp32_psram DT_N_S_soc_S_memory_3c000000_S_psram0
#define DT_N_NODELABEL_psram0             DT_N_S_soc_S_memory_3c000000_S_psram0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_REG_NUM 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_REG(fn) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_REG_SEP(fn, sep) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_REG_VARGS(fn, ...) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_REG_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_RANGES_NUM 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_memory_3c000000_S_psram0_IRQ_NUM 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_IRQ_LEVEL 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_COMPAT_MATCHES_espressif_esp32_psram 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_memory_3c000000_S_psram0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_COMPAT_MODEL_IDX_0 "esp32-psram"
#define DT_N_S_soc_S_memory_3c000000_S_psram0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_size 8388608
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_size_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible {"espressif,esp32-psram"}
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_IDX_0 "espressif,esp32-psram"
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-psram
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_psram
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_PSRAM
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, compatible, 0)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, compatible, 0)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_LEN 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_wakeup_source 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_memory_3c000000_S_psram0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sdhc@60028000
 *
 * Node identifier: DT_N_S_soc_S_sdhc_60028000
 *
 * Binding (compatible = espressif,esp32-sdhc):
 *   $ZEPHYR_BASE/dts/bindings/sdhc/espressif,esp32-sdhc.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sdhc_60028000_PATH "/soc/sdhc@60028000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sdhc_60028000_FULL_NAME "sdhc@60028000"
#define DT_N_S_soc_S_sdhc_60028000_FULL_NAME_UNQUOTED sdhc@60028000
#define DT_N_S_soc_S_sdhc_60028000_FULL_NAME_TOKEN sdhc_60028000
#define DT_N_S_soc_S_sdhc_60028000_FULL_NAME_UPPER_TOKEN SDHC_60028000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_sdhc_60028000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sdhc_60028000_CHILD_IDX 45

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sdhc_60028000_NODELABEL_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_NODELABEL(fn) fn(sdhc)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_NODELABEL_VARGS(fn, ...) fn(sdhc, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sdhc_60028000_CHILD_NUM 2
#define DT_N_S_soc_S_sdhc_60028000_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sdhc_60028000_CHILD_UNIT_ADDR_INT_0 DT_N_S_soc_S_sdhc_60028000_S_sdhc_0
#define DT_N_S_soc_S_sdhc_60028000_CHILD_UNIT_ADDR_INT_1 DT_N_S_soc_S_sdhc_60028000_S_sdhc_1
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sdhc_60028000_HASH WJtDE45zWV_jEwc5NTc5y16NyjYaQaA876gtLI8QBJQ

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sdhc_60028000_ORD 100
#define DT_N_S_soc_S_sdhc_60028000_ORD_STR_SORTABLE 00100

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sdhc_60028000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sdhc_60028000_SUPPORTS_ORDS \
	101, /* /soc/sdhc@60028000/sdhc@0 */ \
	102, /* /soc/sdhc@60028000/sdhc@1 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sdhc_60028000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_sdhc DT_N_S_soc_S_sdhc_60028000
#define DT_N_NODELABEL_sdhc              DT_N_S_soc_S_sdhc_60028000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sdhc_60028000_REG_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_REG_IDX_0_VAL_ADDRESS 1610776576 /* 0x60028000 */
#define DT_N_S_soc_S_sdhc_60028000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_REG(fn) fn(DT_N_S_soc_S_sdhc_60028000, 0)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000, 0)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_RANGES_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sdhc_60028000_IRQ_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_irq 30
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_sdhc_60028000_IRQ_LEVEL 1
#define DT_N_S_soc_S_sdhc_60028000_COMPAT_MATCHES_espressif_esp32_sdhc 1
#define DT_N_S_soc_S_sdhc_60028000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_sdhc_60028000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_COMPAT_MODEL_IDX_0 "esp32-sdhc"
#define DT_N_S_soc_S_sdhc_60028000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sdhc_60028000_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sdhc_60028000_P_reg {1610776576 /* 0x60028000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_sdhc_60028000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_reg_IDX_0 1610776576
#define DT_N_S_soc_S_sdhc_60028000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_sdhc_60028000_P_reg_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts {30 /* 0x1e */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_0 30
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_sdhc_60028000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_compatible {"espressif,esp32-sdhc"}
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_IDX_0 "espressif,esp32-sdhc"
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-sdhc
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_sdhc
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SDHC
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000, interrupt_parent, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000, interrupt_parent, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_VAL_offset 117
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0, offset)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0, offset)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sdhc_60028000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_wakeup_source 0
#define DT_N_S_soc_S_sdhc_60028000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sdhc_60028000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sdhc@60028000/sdhc@0
 *
 * Node identifier: DT_N_S_soc_S_sdhc_60028000_S_sdhc_0
 *
 * Binding (compatible = espressif,esp32-sdhc-slot):
 *   $ZEPHYR_BASE/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_PATH "/soc/sdhc@60028000/sdhc@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FULL_NAME "sdhc@0"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FULL_NAME_UNQUOTED sdhc@0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FULL_NAME_TOKEN sdhc_0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FULL_NAME_UPPER_TOKEN SDHC_0

/* Node parent (/soc/sdhc@60028000) identifier: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_PARENT DT_N_S_soc_S_sdhc_60028000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_NODELABEL(fn) fn(sdhc0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(sdhc0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_CHILD_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_HASH he1VhJo12kFC25I3bHsbaMju2U2hVQi6vxbE_SrflSE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_ORD 101
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_ORD_STR_SORTABLE 00101

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_REQUIRES_ORDS \
	100, /* /soc/sdhc@60028000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_EXISTS 1
#define DT_N_INST_0_espressif_esp32_sdhc_slot DT_N_S_soc_S_sdhc_60028000_S_sdhc_0
#define DT_N_NODELABEL_sdhc0                  DT_N_S_soc_S_sdhc_60028000_S_sdhc_0

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_REG_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_RANGES_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_IRQ_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_COMPAT_MATCHES_espressif_esp32_sdhc_slot 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_COMPAT_MODEL_IDX_0 "esp32-sdhc-slot"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width 4
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width_IDX_0_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_bus_width_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_330 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_330_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_300 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_300_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_180 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_current_180_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_bus_freq 400000
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_max_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_min_bus_freq 400000
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_min_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_power_delay_ms 500
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_power_delay_ms_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_mmc_hs200_1_8v 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_mmc_hs200_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_mmc_hs400_1_8v 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_mmc_hs400_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status "disabled"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, status, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, status, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_status_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible {"espressif,esp32-sdhc-slot"}
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_IDX_0 "espressif,esp32-sdhc-slot"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-sdhc-slot
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_sdhc_slot
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SDHC_SLOT
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_wakeup_source 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/sdhc@60028000/sdhc@1
 *
 * Node identifier: DT_N_S_soc_S_sdhc_60028000_S_sdhc_1
 *
 * Binding (compatible = espressif,esp32-sdhc-slot):
 *   $ZEPHYR_BASE/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_PATH "/soc/sdhc@60028000/sdhc@1"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FULL_NAME "sdhc@1"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FULL_NAME_UNQUOTED sdhc@1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FULL_NAME_TOKEN sdhc_1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FULL_NAME_UPPER_TOKEN SDHC_1

/* Node parent (/soc/sdhc@60028000) identifier: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_PARENT DT_N_S_soc_S_sdhc_60028000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_CHILD_IDX 1

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_NODELABEL_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_NODELABEL(fn) fn(sdhc1)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_NODELABEL_VARGS(fn, ...) fn(sdhc1, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_CHILD_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_HASH OGL36AVbkrJ6dOb6zg3yj9wHCe0Htuq2s5hJ9PP5L7M

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_ORD 102
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_ORD_STR_SORTABLE 00102

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_REQUIRES_ORDS \
	100, /* /soc/sdhc@60028000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_EXISTS 1
#define DT_N_INST_1_espressif_esp32_sdhc_slot DT_N_S_soc_S_sdhc_60028000_S_sdhc_1
#define DT_N_NODELABEL_sdhc1                  DT_N_S_soc_S_sdhc_60028000_S_sdhc_1

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_REG_NUM 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_REG(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_RANGES_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_IRQ_NUM 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_IRQ_LEVEL 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_COMPAT_MATCHES_espressif_esp32_sdhc_slot 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_COMPAT_MODEL_IDX_0 "esp32-sdhc-slot"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_STATUS_disabled 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_reg {1 /* 0x1 */}
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_reg_IDX_0 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_reg_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width 4
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width_IDX_0_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width_ENUM_VAL_4_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_bus_width_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_330 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_330_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_300 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_300_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_180 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_current_180_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_bus_freq 400000
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_max_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_min_bus_freq 400000
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_min_bus_freq_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_power_delay_ms 500
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_power_delay_ms_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_mmc_hs200_1_8v 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_mmc_hs200_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_mmc_hs400_1_8v 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_mmc_hs400_1_8v_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status "disabled"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_STRING_UNQUOTED disabled
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_STRING_TOKEN disabled
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_STRING_UPPER_TOKEN DISABLED
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_IDX_0 "disabled"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_IDX_0_ENUM_IDX 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_ENUM_VAL_disabled_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, status, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, status, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_status_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible {"espressif,esp32-sdhc-slot"}
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_IDX_0 "espressif,esp32-sdhc-slot"
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-sdhc-slot
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_sdhc_slot
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SDHC_SLOT
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, compatible, 0)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_LEN 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_compatible_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_wakeup_source 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_sdhc_60028000_S_sdhc_1_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@60024000
 *
 * Node identifier: DT_N_S_soc_S_spi_60024000
 *
 * Binding (compatible = espressif,esp32-spi):
 *   $ZEPHYR_BASE/dts/bindings/spi/espressif,esp32-spi.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_60024000_PATH "/soc/spi@60024000"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_60024000_FULL_NAME "spi@60024000"
#define DT_N_S_soc_S_spi_60024000_FULL_NAME_UNQUOTED spi@60024000
#define DT_N_S_soc_S_spi_60024000_FULL_NAME_TOKEN spi_60024000
#define DT_N_S_soc_S_spi_60024000_FULL_NAME_UPPER_TOKEN SPI_60024000

/* Node parent (/soc) identifier: */
#define DT_N_S_soc_S_spi_60024000_PARENT DT_N_S_soc

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_60024000_CHILD_IDX 24

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_60024000_NODELABEL_NUM 2
#define DT_N_S_soc_S_spi_60024000_FOREACH_NODELABEL(fn) fn(spi2) fn(xiao_spi)
#define DT_N_S_soc_S_spi_60024000_FOREACH_NODELABEL_VARGS(fn, ...) fn(spi2, __VA_ARGS__) fn(xiao_spi, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_60024000_CHILD_NUM 1
#define DT_N_S_soc_S_spi_60024000_CHILD_NUM_STATUS_OKAY 1
#define DT_N_S_soc_S_spi_60024000_CHILD_UNIT_ADDR_INT_0 DT_N_S_soc_S_spi_60024000_S_lora_0
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__)

/* Node's hash: */
#define DT_N_S_soc_S_spi_60024000_HASH cAnuUIWiVpDjQN_NLMvQuebfun49HKk2_1TcBDFx2SE

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_60024000_ORD 103
#define DT_N_S_soc_S_spi_60024000_ORD_STR_SORTABLE 00103

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_60024000_REQUIRES_ORDS \
	12, /* /soc */ \
	14, /* /soc/interrupt-controller@600c2000 */ \
	15, /* /soc/gpio/gpio@60004000 */ \
	26, /* /pin-controller/spim2_default */ \
	34, /* /clock */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_60024000_SUPPORTS_ORDS \
	104, /* /soc/spi@60024000/lora@0 */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_60024000_EXISTS 1
#define DT_N_INST_0_espressif_esp32_spi DT_N_S_soc_S_spi_60024000
#define DT_N_NODELABEL_spi2             DT_N_S_soc_S_spi_60024000
#define DT_N_NODELABEL_xiao_spi         DT_N_S_soc_S_spi_60024000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_60024000_REG_NUM 1
#define DT_N_S_soc_S_spi_60024000_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_REG_IDX_0_VAL_ADDRESS 1610760192 /* 0x60024000 */
#define DT_N_S_soc_S_spi_60024000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */
#define DT_N_S_soc_S_spi_60024000_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_60024000, 0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, 0)
#define DT_N_S_soc_S_spi_60024000_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_RANGES_NUM 0
#define DT_N_S_soc_S_spi_60024000_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_60024000_IRQ_NUM 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_irq 21
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_irq_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_priority 0
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_priority_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60024000_IRQ_LEVEL 1
#define DT_N_S_soc_S_spi_60024000_COMPAT_MATCHES_espressif_esp32_spi 1
#define DT_N_S_soc_S_spi_60024000_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_COMPAT_VENDOR_IDX_0 "Espressif Systems"
#define DT_N_S_soc_S_spi_60024000_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_COMPAT_MODEL_IDX_0 "esp32-spi"
#define DT_N_S_soc_S_spi_60024000_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_60024000_PINCTRL_NUM 1
#define DT_N_S_soc_S_spi_60024000_PINCTRL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_PINCTRL_IDX_0_TOKEN default
#define DT_N_S_soc_S_spi_60024000_PINCTRL_IDX_0_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_60024000_PINCTRL_NAME_default_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_PINCTRL_NAME_default_IDX 0
#define DT_N_S_soc_S_spi_60024000_PINCTRL_NAME_default_IDX_0_PH DT_N_S_pin_controller_S_spim2_default

/* Generic property macros: */
#define DT_N_S_soc_S_spi_60024000_P_reg {1610760192 /* 0x60024000 */, 4096 /* 0x1000 */}
#define DT_N_S_soc_S_spi_60024000_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_reg_IDX_0 1610760192
#define DT_N_S_soc_S_spi_60024000_P_reg_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_reg_IDX_1 4096
#define DT_N_S_soc_S_spi_60024000_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_IDX_0 DT_N_S_pin_controller_S_spim2_default
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_IDX_0_PH DT_N_S_pin_controller_S_spim2_default
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, pinctrl_0, 0)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, pinctrl_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names {"default"}
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_IDX_0 "default"
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_IDX_0_STRING_TOKEN default
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, pinctrl_names, 0)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, pinctrl_names, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_pinctrl_names_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_half_duplex 0
#define DT_N_S_soc_S_spi_60024000_P_half_duplex_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_dummy_comp 0
#define DT_N_S_soc_S_spi_60024000_P_dummy_comp_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_sio 0
#define DT_N_S_soc_S_spi_60024000_P_sio_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_dma_enabled 0
#define DT_N_S_soc_S_spi_60024000_P_dma_enabled_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_dma_host 0
#define DT_N_S_soc_S_spi_60024000_P_dma_host_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_clk_as_cs 0
#define DT_N_S_soc_S_spi_60024000_P_clk_as_cs_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_positive_cs 0
#define DT_N_S_soc_S_spi_60024000_P_positive_cs_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_use_iomux 0
#define DT_N_S_soc_S_spi_60024000_P_use_iomux_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_line_idle_low 0
#define DT_N_S_soc_S_spi_60024000_P_line_idle_low_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_VAL_pin 3
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, cs_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_cs_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_status "okay"
#define DT_N_S_soc_S_spi_60024000_P_status_STRING_UNQUOTED okay
#define DT_N_S_soc_S_spi_60024000_P_status_STRING_TOKEN okay
#define DT_N_S_soc_S_spi_60024000_P_status_STRING_UPPER_TOKEN OKAY
#define DT_N_S_soc_S_spi_60024000_P_status_IDX_0 "okay"
#define DT_N_S_soc_S_spi_60024000_P_status_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_status_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_60024000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_status_ENUM_VAL_okay_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, status, 0)
#define DT_N_S_soc_S_spi_60024000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, status, 0)
#define DT_N_S_soc_S_spi_60024000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, status, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_status_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_status_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_compatible {"espressif,esp32-spi"}
#define DT_N_S_soc_S_spi_60024000_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_compatible_IDX_0 "espressif,esp32-spi"
#define DT_N_S_soc_S_spi_60024000_P_compatible_IDX_0_STRING_UNQUOTED espressif,esp32-spi
#define DT_N_S_soc_S_spi_60024000_P_compatible_IDX_0_STRING_TOKEN espressif_esp32_spi
#define DT_N_S_soc_S_spi_60024000_P_compatible_IDX_0_STRING_UPPER_TOKEN ESPRESSIF_ESP32_SPI
#define DT_N_S_soc_S_spi_60024000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, compatible, 0)
#define DT_N_S_soc_S_spi_60024000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, compatible, 0)
#define DT_N_S_soc_S_spi_60024000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupts {21 /* 0x15 */, 0 /* 0x0 */, 0 /* 0x0 */}
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_0 21
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_1_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_1 0
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_2_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupts_IDX_2 0
#define DT_N_S_soc_S_spi_60024000_P_interrupts_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_IDX_0 DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_IDX_0_PH DT_N_S_soc_S_interrupt_controller_600c2000
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, interrupt_parent, 0)
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, interrupt_parent, 0)
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, interrupt_parent, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_interrupt_parent_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_PH DT_N_S_clock
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_VAL_offset 115
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_VAL_offset_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000, clocks, 0, offset)
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, clocks, 0, offset)
#define DT_N_S_soc_S_spi_60024000_P_clocks_IDX_0_NUM_CELLS 1
#define DT_N_S_soc_S_spi_60024000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000, clocks, 0)
#define DT_N_S_soc_S_spi_60024000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000, clocks, 0)
#define DT_N_S_soc_S_spi_60024000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000, clocks, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_P_clocks_LEN 1
#define DT_N_S_soc_S_spi_60024000_P_clocks_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_60024000_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_wakeup_source 0
#define DT_N_S_soc_S_spi_60024000_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_60024000_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Devicetree node: /soc/spi@60024000/lora@0
 *
 * Node identifier: DT_N_S_soc_S_spi_60024000_S_lora_0
 *
 * Binding (compatible = semtech,sx1262):
 *   $ZEPHYR_BASE/dts/bindings/lora/semtech,sx1262.yaml
 *
 * (Descriptions have moved to the Devicetree Bindings Index
 * in the documentation.)
 */

/* Node's full path: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_PATH "/soc/spi@60024000/lora@0"

/* Node's name with unit-address: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FULL_NAME "lora@0"
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FULL_NAME_UNQUOTED lora@0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FULL_NAME_TOKEN lora_0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FULL_NAME_UPPER_TOKEN LORA_0

/* Node parent (/soc/spi@60024000) identifier: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_PARENT DT_N_S_soc_S_spi_60024000

/* Node's index in its parent's list of children: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_CHILD_IDX 0

/* Helpers for dealing with node labels: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_NODELABEL_NUM 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_NODELABEL(fn) fn(lora)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_NODELABEL_VARGS(fn, ...) fn(lora, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_ANCESTOR(fn) fn(DT_N_S_soc_S_spi_60024000) fn(DT_N_S_soc) fn(DT_N)

/* Helper macros for child nodes of this node. */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_CHILD_NUM 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_CHILD_NUM_STATUS_OKAY 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD(fn) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_STATUS_OKAY(fn) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) 

/* Node's hash: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_HASH Cpi5_SzclALqN1V71JzhFL2_OAvIZubOdG6r_xRoO7I

/* Node's dependency ordinal: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_ORD 104
#define DT_N_S_soc_S_spi_60024000_S_lora_0_ORD_STR_SORTABLE 00104

/* Ordinals for what this node depends on directly: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_REQUIRES_ORDS \
	15, /* /soc/gpio/gpio@60004000 */ \
	103, /* /soc/spi@60024000 */

/* Ordinals for what depends directly on this node: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_SUPPORTS_ORDS /* nothing */

/* Existence and alternate IDs: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_EXISTS 1
#define DT_N_ALIAS_lora0           DT_N_S_soc_S_spi_60024000_S_lora_0
#define DT_N_INST_0_semtech_sx1262 DT_N_S_soc_S_spi_60024000_S_lora_0
#define DT_N_NODELABEL_lora        DT_N_S_soc_S_spi_60024000_S_lora_0

/* Bus info (controller: '/soc/spi@60024000', type: '['spi']') */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_BUS_spi 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_BUS DT_N_S_soc_S_spi_60024000

/* Macros for properties that are special in the specification: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_REG_NUM 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_REG_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_REG(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_REG_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_REG_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_REG_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_RANGES_NUM 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_FOREACH_RANGE(fn) 
#define DT_N_S_soc_S_spi_60024000_S_lora_0_IRQ_NUM 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_IRQ_LEVEL 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_COMPAT_MATCHES_semtech_sx1262 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_COMPAT_VENDOR_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_COMPAT_VENDOR_IDX_0 "Semtech Corporation"
#define DT_N_S_soc_S_spi_60024000_S_lora_0_COMPAT_MODEL_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_COMPAT_MODEL_IDX_0 "sx1262"
#define DT_N_S_soc_S_spi_60024000_S_lora_0_STATUS_okay 1

/* Pin control (pinctrl-<i>, pinctrl-names) properties: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_PINCTRL_NUM 0

/* Generic property macros: */
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_VAL_pin 2
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_VAL_flags 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, reset_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_LEN 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reset_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_VAL_pin 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, busy_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_LEN 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_busy_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_VAL_pin 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, dio1_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_LEN 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio1_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_PH DT_N_S_soc_S_gpio_S_gpio_60004000
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_VAL_pin 4
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_VAL_pin_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_VAL_flags 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_VAL_flags_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_FOREACH_CELL(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, pin) \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_FOREACH_CELL_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, pin) DT_DEBRACKET_INTERNAL sep \
	fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, flags)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_IDX_0_NUM_CELLS 2
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, tx_enable_gpios, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_LEN 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_tx_enable_gpios_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio2_tx_enable 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_dio2_tx_enable_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_rx_boosted 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_rx_boosted_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_regulator_ldo 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_regulator_ldo_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_force_ldro 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_force_ldro_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reg {0 /* 0x0 */}
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reg_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reg_IDX_0 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_reg_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_max_frequency 4000000
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_max_frequency_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_duplex_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format_IDX_0_ENUM_IDX 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format_IDX_0_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format_ENUM_VAL_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_frame_format_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cpol 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cpol_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cpha 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cpha_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_lsb_first 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_lsb_first_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_hold_cs 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_hold_cs_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cs_high 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_cs_high_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_interframe_delay_ns 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_spi_interframe_delay_ns_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible {"semtech,sx1262"}
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_IDX_0_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_IDX_0 "semtech,sx1262"
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_IDX_0_STRING_UNQUOTED semtech,sx1262
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_IDX_0_STRING_TOKEN semtech_sx1262
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_IDX_0_STRING_UPPER_TOKEN SEMTECH_SX1262
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, compatible, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, compatible, 0)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, compatible, 0, __VA_ARGS__)
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_LEN 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_compatible_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_zephyr_deferred_init 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_zephyr_deferred_init_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_wakeup_source 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_wakeup_source_EXISTS 1
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_zephyr_pm_device_runtime_auto 0
#define DT_N_S_soc_S_spi_60024000_S_lora_0_P_zephyr_pm_device_runtime_auto_EXISTS 1

/*
 * Chosen nodes
 */
#define DT_CHOSEN_zephyr_canbus                  DT_N_S_soc_S_can_6002b000
#define DT_CHOSEN_zephyr_canbus_EXISTS           1
#define DT_CHOSEN_zephyr_entropy                 DT_N_S_soc_S_trng_6003507c
#define DT_CHOSEN_zephyr_entropy_EXISTS          1
#define DT_CHOSEN_zephyr_flash_controller        DT_N_S_soc_S_flash_controller_60002000
#define DT_CHOSEN_zephyr_flash_controller_EXISTS 1
#define DT_CHOSEN_zephyr_sram                    DT_N_S_soc_S_memory_3fc88000
#define DT_CHOSEN_zephyr_sram_EXISTS             1
#define DT_CHOSEN_zephyr_console                 DT_N_S_soc_S_uart_60038000
#define DT_CHOSEN_zephyr_console_EXISTS          1
#define DT_CHOSEN_zephyr_shell_uart              DT_N_S_soc_S_uart_60038000
#define DT_CHOSEN_zephyr_shell_uart_EXISTS       1
#define DT_CHOSEN_zephyr_flash                   DT_N_S_soc_S_flash_controller_60002000_S_flash_0
#define DT_CHOSEN_zephyr_flash_EXISTS            1
#define DT_CHOSEN_zephyr_code_partition          DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
#define DT_CHOSEN_zephyr_bt_hci                  DT_N_S_esp32_bt_hci
#define DT_CHOSEN_zephyr_bt_hci_EXISTS           1
#define DT_CHOSEN_loramodem_kiss_uart            DT_N_S_soc_S_uart_60038000
#define DT_CHOSEN_loramodem_kiss_uart_EXISTS     1

/* Macros for iterating over all nodes and enabled nodes */
#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_memory_42000000) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc_S_memory_3c000000_S_psram0) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_3fce5000) fn(DT_N_S_soc_S_memory_3fce5400) fn(DT_N_S_soc_S_ipm_3fce9400) fn(DT_N_S_soc_S_mbox_3fce9408) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000) fn(DT_N_S_soc_S_interrupt_controller_600c2000) fn(DT_N_S_soc_S_xt_wdt_60021004) fn(DT_N_S_soc_S_rtc_timer_60008004) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000) fn(DT_N_S_soc_S_uart_60000000) fn(DT_N_S_soc_S_uart_60010000) fn(DT_N_S_soc_S_uart_6002e000) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) fn(DT_N_S_soc_S_gpio_S_gpio_60004800) fn(DT_N_S_soc_S_touch_6000885c) fn(DT_N_S_soc_S_i2c_60013000) fn(DT_N_S_soc_S_i2c_60027000) fn(DT_N_S_soc_S_i2s_6000f000) fn(DT_N_S_soc_S_i2s_6002d000) fn(DT_N_S_soc_S_spi_60024000) fn(DT_N_S_soc_S_spi_60024000_S_lora_0) fn(DT_N_S_soc_S_spi_60025000) fn(DT_N_S_soc_S_coretemp_60008800) fn(DT_N_S_soc_S_adc_60040000) fn(DT_N_S_soc_S_adc_60040004) fn(DT_N_S_soc_S_can_6002b000) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp) fn(DT_N_S_soc_S_uart_60038000) fn(DT_N_S_soc_S_usb_otg_60080000) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc_S_counter_6001f000_S_counter) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc_S_counter_6001f024_S_counter) fn(DT_N_S_soc_S_counter_60020000) fn(DT_N_S_soc_S_counter_60020000_S_counter) fn(DT_N_S_soc_S_counter_60020024) fn(DT_N_S_soc_S_counter_60020024_S_counter) fn(DT_N_S_soc_S_watchdog_6001f048) fn(DT_N_S_soc_S_watchdog_60020048) fn(DT_N_S_soc_S_trng_6003507c) fn(DT_N_S_soc_S_ledc_60019000) fn(DT_N_S_soc_S_mcpwm_6001e000) fn(DT_N_S_soc_S_mcpwm_6002c000) fn(DT_N_S_soc_S_pcnt_60017000) fn(DT_N_S_soc_S_dma_6003f000) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1) fn(DT_N_S_soc_S_sha_6003b000) fn(DT_N_S_soc_S_aes_6003a000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_1) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_light_sleep) fn(DT_N_S_cpus_S_power_states_S_deep_sleep) fn(DT_N_S_wifi) fn(DT_N_S_esp32_bt_hci) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) fn(DT_N_S_pin_controller_S_spim2_default_S_group2) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2) fn(DT_N_S_pin_controller_S_twai_default) fn(DT_N_S_pin_controller_S_twai_default_S_group1) fn(DT_N_S_clock) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0)
#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_memory_42000000) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc_S_memory_3c000000_S_psram0) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_3fce5000) fn(DT_N_S_soc_S_memory_3fce5400) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000) fn(DT_N_S_soc_S_interrupt_controller_600c2000) fn(DT_N_S_soc_S_flash_controller_60002000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000) fn(DT_N_S_soc_S_uart_60000000) fn(DT_N_S_soc_S_gpio) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) fn(DT_N_S_soc_S_gpio_S_gpio_60004800) fn(DT_N_S_soc_S_i2c_60013000) fn(DT_N_S_soc_S_spi_60024000) fn(DT_N_S_soc_S_spi_60024000_S_lora_0) fn(DT_N_S_soc_S_lcd_cam_60041000) fn(DT_N_S_soc_S_uart_60038000) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc_S_counter_60020024) fn(DT_N_S_soc_S_watchdog_6001f048) fn(DT_N_S_soc_S_trng_6003507c) fn(DT_N_S_soc_S_sdhc_60028000) fn(DT_N_S_soc_S_sha_6003b000) fn(DT_N_S_soc_S_aes_6003a000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_1) fn(DT_N_S_cpus_S_power_states) fn(DT_N_S_cpus_S_power_states_S_light_sleep) fn(DT_N_S_wifi) fn(DT_N_S_esp32_bt_hci) fn(DT_N_S_pin_controller) fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2) fn(DT_N_S_pin_controller_S_spim2_default) fn(DT_N_S_pin_controller_S_spim2_default_S_group1) fn(DT_N_S_pin_controller_S_spim2_default_S_group2) fn(DT_N_S_pin_controller_S_i2c0_default) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2) fn(DT_N_S_pin_controller_S_twai_default) fn(DT_N_S_pin_controller_S_twai_default_S_group1) fn(DT_N_S_clock) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0)
#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) fn(DT_N_S_soc_S_ipm_3fce9400, __VA_ARGS__) fn(DT_N_S_soc_S_mbox_3fce9408, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) fn(DT_N_S_soc_S_xt_wdt_60021004, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_timer_60008004, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60010000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_6002e000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__) fn(DT_N_S_soc_S_touch_6000885c, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60027000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_6000f000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_6002d000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60025000, __VA_ARGS__) fn(DT_N_S_soc_S_coretemp_60008800, __VA_ARGS__) fn(DT_N_S_soc_S_adc_60040000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_60040004, __VA_ARGS__) fn(DT_N_S_soc_S_can_6002b000, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_dvp, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000_S_lcd_cam_disp, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_otg_60080000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_60020048, __VA_ARGS__) fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) fn(DT_N_S_soc_S_ledc_60019000, __VA_ARGS__) fn(DT_N_S_soc_S_mcpwm_6001e000, __VA_ARGS__) fn(DT_N_S_soc_S_mcpwm_6002c000, __VA_ARGS__) fn(DT_N_S_soc_S_pcnt_60017000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_6003f000, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_0, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000_S_sdhc_1, __VA_ARGS__) fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_deep_sleep, __VA_ARGS__) fn(DT_N_S_wifi, __VA_ARGS__) fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__) fn(DT_N_S_clock, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__) fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__) fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__) fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__) fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__) fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__) fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states, __VA_ARGS__) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__) fn(DT_N_S_wifi, __VA_ARGS__) fn(DT_N_S_esp32_bt_hci, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spim2_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_lcd_cam_default_S_group2, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_twai_default_S_group1, __VA_ARGS__) fn(DT_N_S_clock, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__)
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_0
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_sys DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_10000
#define DT_COMPAT_fixed_partitions_LABEL_sys_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_20000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1 DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_170000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0_appcpu DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_2c0000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_appcpu_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1_appcpu DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_330000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_appcpu_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_0_lpcore DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a0000
#define DT_COMPAT_fixed_partitions_LABEL_image_0_lpcore_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_1_lpcore DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3a8000
#define DT_COMPAT_fixed_partitions_LABEL_image_1_lpcore_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_storage DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3b0000
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3e0000
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS 1
#define DT_COMPAT_fixed_partitions_LABEL_coredump DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions_S_partition_3ff000
#define DT_COMPAT_fixed_partitions_LABEL_coredump_EXISTS 1

/*
 * Macros for compatibles with status "okay" nodes
 */
#define DT_COMPAT_HAS_OKAY_seeed_xiao_esp32s3 1
#define DT_COMPAT_HAS_OKAY_simple_bus 1
#define DT_COMPAT_HAS_OKAY_zephyr_memory_region 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_psram 1
#define DT_COMPAT_HAS_OKAY_mmio_sram 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_intc 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_flash_controller 1
#define DT_COMPAT_HAS_OKAY_soc_nv_flash 1
#define DT_COMPAT_HAS_OKAY_fixed_partitions 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_uart 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_gpio 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_i2c 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_spi 1
#define DT_COMPAT_HAS_OKAY_semtech_sx1262 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_lcd_cam 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_usb_serial 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_timer 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_watchdog 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_trng 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_sdhc 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_sha 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_aes 1
#define DT_COMPAT_HAS_OKAY_espressif_xtensa_lx7 1
#define DT_COMPAT_HAS_OKAY_zephyr_power_state 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_wifi 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_bt_hci 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_pinctrl 1
#define DT_COMPAT_HAS_OKAY_espressif_esp32_clock 1
#define DT_COMPAT_HAS_OKAY_seeed_xiao_gpio 1
#define DT_COMPAT_HAS_OKAY_gpio_leds 1

/*
 * Macros for status "okay" instances of each compatible
 */
#define DT_N_INST_seeed_xiao_esp32s3_NUM_OKAY 1
#define DT_N_INST_simple_bus_NUM_OKAY 2
#define DT_N_INST_zephyr_memory_region_NUM_OKAY 7
#define DT_N_INST_espressif_esp32_psram_NUM_OKAY 1
#define DT_N_INST_mmio_sram_NUM_OKAY 7
#define DT_N_INST_espressif_esp32_intc_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_flash_controller_NUM_OKAY 1
#define DT_N_INST_soc_nv_flash_NUM_OKAY 1
#define DT_N_INST_fixed_partitions_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_uart_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_gpio_NUM_OKAY 2
#define DT_N_INST_espressif_esp32_i2c_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_spi_NUM_OKAY 1
#define DT_N_INST_semtech_sx1262_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_lcd_cam_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_usb_serial_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_timer_NUM_OKAY 3
#define DT_N_INST_espressif_esp32_watchdog_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_trng_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_sdhc_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_sha_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_aes_NUM_OKAY 1
#define DT_N_INST_espressif_xtensa_lx7_NUM_OKAY 2
#define DT_N_INST_zephyr_power_state_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_wifi_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_bt_hci_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_pinctrl_NUM_OKAY 1
#define DT_N_INST_espressif_esp32_clock_NUM_OKAY 1
#define DT_N_INST_seeed_xiao_gpio_NUM_OKAY 1
#define DT_N_INST_gpio_leds_NUM_OKAY 1
#define DT_FOREACH_OKAY_seeed_xiao_esp32s3(fn) fn(DT_N)
#define DT_FOREACH_OKAY_VARGS_seeed_xiao_esp32s3(fn, ...) fn(DT_N, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_seeed_xiao_esp32s3(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_seeed_xiao_esp32s3(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_simple_bus(fn) fn(DT_N_S_soc) fn(DT_N_S_soc_S_gpio)
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_gpio, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_simple_bus(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_memory_region(fn) fn(DT_N_S_soc_S_memory_42000000) fn(DT_N_S_soc_S_memory_3c000000) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000)
#define DT_FOREACH_OKAY_VARGS_zephyr_memory_region(fn, ...) fn(DT_N_S_soc_S_memory_42000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3c000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_memory_region(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) fn(6)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_memory_region(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) fn(6, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_psram(fn) fn(DT_N_S_soc_S_memory_3c000000_S_psram0)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_psram(fn, ...) fn(DT_N_S_soc_S_memory_3c000000_S_psram0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_psram(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_psram(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_mmio_sram(fn) fn(DT_N_S_soc_S_memory_40370000) fn(DT_N_S_soc_S_memory_3fc88000) fn(DT_N_S_soc_S_memory_3fcf0000) fn(DT_N_S_soc_S_memory_3fce5000) fn(DT_N_S_soc_S_memory_3fce5400) fn(DT_N_S_soc_S_memory_50000000) fn(DT_N_S_soc_S_memory_600fe000)
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...) fn(DT_N_S_soc_S_memory_40370000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fc88000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fcf0000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_3fce5400, __VA_ARGS__) fn(DT_N_S_soc_S_memory_50000000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_600fe000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_mmio_sram(fn) fn(0) fn(1) fn(2) fn(3) fn(4) fn(5) fn(6)
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__) fn(6, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_intc(fn) fn(DT_N_S_soc_S_interrupt_controller_600c2000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_intc(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_600c2000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_intc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_intc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_flash_controller(fn) fn(DT_N_S_soc_S_flash_controller_60002000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_flash_controller(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_flash_controller(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_flash_controller(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_soc_nv_flash(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0)
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_fixed_partitions(fn) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions)
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...) fn(DT_N_S_soc_S_flash_controller_60002000_S_flash_0_S_partitions, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_uart(fn) fn(DT_N_S_soc_S_uart_60000000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_uart(fn, ...) fn(DT_N_S_soc_S_uart_60000000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_uart(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_uart(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_gpio(fn) fn(DT_N_S_soc_S_gpio_S_gpio_60004000) fn(DT_N_S_soc_S_gpio_S_gpio_60004800)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_gpio(fn, ...) fn(DT_N_S_soc_S_gpio_S_gpio_60004000, __VA_ARGS__) fn(DT_N_S_soc_S_gpio_S_gpio_60004800, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_gpio(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_gpio(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_i2c(fn) fn(DT_N_S_soc_S_i2c_60013000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_i2c(fn, ...) fn(DT_N_S_soc_S_i2c_60013000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_i2c(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_i2c(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_spi(fn) fn(DT_N_S_soc_S_spi_60024000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_spi(fn, ...) fn(DT_N_S_soc_S_spi_60024000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_spi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_spi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_semtech_sx1262(fn) fn(DT_N_S_soc_S_spi_60024000_S_lora_0)
#define DT_FOREACH_OKAY_VARGS_semtech_sx1262(fn, ...) fn(DT_N_S_soc_S_spi_60024000_S_lora_0, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_semtech_sx1262(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_semtech_sx1262(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_lcd_cam(fn) fn(DT_N_S_soc_S_lcd_cam_60041000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_lcd_cam(fn, ...) fn(DT_N_S_soc_S_lcd_cam_60041000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_lcd_cam(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_lcd_cam(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_usb_serial(fn) fn(DT_N_S_soc_S_uart_60038000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_usb_serial(fn, ...) fn(DT_N_S_soc_S_uart_60038000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_usb_serial(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_usb_serial(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_timer(fn) fn(DT_N_S_soc_S_counter_6001f000) fn(DT_N_S_soc_S_counter_6001f024) fn(DT_N_S_soc_S_counter_60020024)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_timer(fn, ...) fn(DT_N_S_soc_S_counter_6001f000, __VA_ARGS__) fn(DT_N_S_soc_S_counter_6001f024, __VA_ARGS__) fn(DT_N_S_soc_S_counter_60020024, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_timer(fn) fn(0) fn(1) fn(2)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_timer(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_watchdog(fn) fn(DT_N_S_soc_S_watchdog_6001f048)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_watchdog(fn, ...) fn(DT_N_S_soc_S_watchdog_6001f048, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_watchdog(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_watchdog(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_trng(fn) fn(DT_N_S_soc_S_trng_6003507c)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_trng(fn, ...) fn(DT_N_S_soc_S_trng_6003507c, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_trng(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_trng(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_sdhc(fn) fn(DT_N_S_soc_S_sdhc_60028000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_sdhc(fn, ...) fn(DT_N_S_soc_S_sdhc_60028000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_sdhc(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_sdhc(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_sha(fn) fn(DT_N_S_soc_S_sha_6003b000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_sha(fn, ...) fn(DT_N_S_soc_S_sha_6003b000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_sha(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_sha(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_aes(fn) fn(DT_N_S_soc_S_aes_6003a000)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_aes(fn, ...) fn(DT_N_S_soc_S_aes_6003a000, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_aes(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_aes(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_xtensa_lx7(fn) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_1)
#define DT_FOREACH_OKAY_VARGS_espressif_xtensa_lx7(fn, ...) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_1, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_xtensa_lx7(fn) fn(0) fn(1)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_xtensa_lx7(fn, ...) fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
#define DT_FOREACH_OKAY_zephyr_power_state(fn) fn(DT_N_S_cpus_S_power_states_S_light_sleep)
#define DT_FOREACH_OKAY_VARGS_zephyr_power_state(fn, ...) fn(DT_N_S_cpus_S_power_states_S_light_sleep, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_zephyr_power_state(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_power_state(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_wifi(fn) fn(DT_N_S_wifi)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_wifi(fn, ...) fn(DT_N_S_wifi, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_wifi(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_wifi(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_bt_hci(fn) fn(DT_N_S_esp32_bt_hci)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_bt_hci(fn, ...) fn(DT_N_S_esp32_bt_hci, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_bt_hci(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_bt_hci(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_pinctrl(fn) fn(DT_N_S_pin_controller)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_pinctrl(fn, ...) fn(DT_N_S_pin_controller, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_pinctrl(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_pinctrl(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_espressif_esp32_clock(fn) fn(DT_N_S_clock)
#define DT_FOREACH_OKAY_VARGS_espressif_esp32_clock(fn, ...) fn(DT_N_S_clock, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_espressif_esp32_clock(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_espressif_esp32_clock(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_seeed_xiao_gpio(fn) fn(DT_N_S_connector)
#define DT_FOREACH_OKAY_VARGS_seeed_xiao_gpio(fn, ...) fn(DT_N_S_connector, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_seeed_xiao_gpio(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_seeed_xiao_gpio(fn, ...) fn(0, __VA_ARGS__)
#define DT_FOREACH_OKAY_gpio_leds(fn) fn(DT_N_S_leds)
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...) fn(DT_N_S_leds, __VA_ARGS__)
#define DT_FOREACH_OKAY_INST_gpio_leds(fn) fn(0)
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...) fn(0, __VA_ARGS__)

/*
 * Bus information for status "okay" nodes of each compatible
 */
#define DT_COMPAT_semtech_sx1262_BUS_spi 1
