#define CONFIG_DT_HAS_ESPRESSIF_ESP32_AES_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_BT_HCI_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_CLOCK_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_FLASH_CONTROLLER_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_GPIO_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_I2C_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_INTC_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_LCD_CAM_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_PINCTRL_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_PSRAM_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_SDHC_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_SHA_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_SPI_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_TIMER_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_TRNG_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_UART_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_USB_SERIAL_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_WATCHDOG_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_ESP32_WIFI_ENABLED 1
#define CONFIG_DT_HAS_ESPRESSIF_XTENSA_LX7_ENABLED 1
#define CONFIG_DT_HAS_FIXED_PARTITIONS_ENABLED 1
#define CONFIG_DT_HAS_GPIO_LEDS_ENABLED 1
#define CONFIG_DT_HAS_MMIO_SRAM_ENABLED 1
#define CONFIG_DT_HAS_SEEED_XIAO_GPIO_ENABLED 1
#define CONFIG_DT_HAS_SEMTECH_SX1262_ENABLED 1
#define CONFIG_DT_HAS_SOC_NV_FLASH_ENABLED 1
#define CONFIG_DT_HAS_ZEPHYR_MEMORY_REGION_ENABLED 1
#define CONFIG_DT_HAS_ZEPHYR_POWER_STATE_ENABLED 1
#define CONFIG_MAIN_STACK_SIZE 2048
#define CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE 1024
#define CONFIG_SERIAL 1
#define CONFIG_SPI 1
#define CONFIG_UART_INTERRUPT_DRIVEN 1
#define CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC 240000000
#define CONFIG_FLASH_SIZE 8388608
#define CONFIG_FLASH_BASE_ADDRESS 0x0
#define CONFIG_MP_MAX_NUM_CPUS 1
#define CONFIG_CLOCK_CONTROL 1
#define CONFIG_IDLE_STACK_SIZE 1024
#define CONFIG_ISR_STACK_SIZE 2048
#define CONFIG_SYS_CLOCK_TICKS_PER_SEC 10000
#define CONFIG_BUILD_OUTPUT_BIN 1
#define CONFIG_ROM_START_OFFSET 0x0
#define CONFIG_KERNEL_ENTRY "__start"
#define CONFIG_HAS_FLASH_LOAD_OFFSET 1
#define CONFIG_TICKLESS_KERNEL 1
#define CONFIG_CLOCK_CONTROL_INIT_PRIORITY 30
#define CONFIG_NUM_METAIRQ_PRIORITIES 0
#define CONFIG_NUM_PREEMPT_PRIORITIES 15
#define CONFIG_DYNAMIC_INTERRUPTS 1
#define CONFIG_GEN_ISR_TABLES 1
#define CONFIG_TIMESLICE_SIZE 20
#define CONFIG_FLASH_LOAD_OFFSET 0x0
#define CONFIG_SYS_CLOCK_EXISTS 1
#define CONFIG_GPIO 1
#define CONFIG_XTENSA_TIMER 1
#define CONFIG_XTENSA_CCOUNT_HZ 240000000
#define CONFIG_LOG 1
#define CONFIG_ARCH_SW_ISR_TABLE_ALIGN 4
#define CONFIG_LOG_DOMAIN_NAME ""
#define CONFIG_LOG_PROCESS_THREAD_STACK_SIZE 1024
#define CONFIG_UART_USE_RUNTIME_CONFIGURE 1
#define CONFIG_CONSOLE 1
#define CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE -1
#define CONFIG_SOC_TOOLCHAIN_NAME "espressif_esp32s3"
#define CONFIG_GEN_SW_ISR_TABLE 1
#define CONFIG_GEN_IRQ_START_VECTOR 0
#define CONFIG_SRAM_OFFSET 0x0
#define CONFIG_XTENSA_TIMER_ID 0
#define CONFIG_XTAL_FREQ_HZ 40000000
#define CONFIG_SOC_FLASH_ESP32 1
#define CONFIG_KERNEL_MEM_POOL 1
#define CONFIG_MULTITHREADING 1
#define CONFIG_LINKER_USE_RELAX 1
#define CONFIG_ZEPHYR_ACPICA_MODULE 1
#define CONFIG_ZEPHYR_CMSIS_MODULE 1
#define CONFIG_ZEPHYR_CMSIS_DSP_MODULE 1
#define CONFIG_ZEPHYR_CMSIS_NN_MODULE 1
#define CONFIG_ZEPHYR_CMSIS_6_MODULE 1
#define CONFIG_ZEPHYR_DHARA_MODULE 1
#define CONFIG_ZEPHYR_FATFS_MODULE 1
#define CONFIG_ZEPHYR_ADI_MODULE 1
#define CONFIG_ZEPHYR_HAL_AFBR_MODULE 1
#define CONFIG_ZEPHYR_HAL_AMBIQ_MODULE 1
#define CONFIG_ZEPHYR_ATMEL_MODULE 1
#define CONFIG_ZEPHYR_HAL_BOUFFALOLAB_MODULE 1
#define CONFIG_ESP_HAL_LOG_LEVEL_DEFAULT 1
#define CONFIG_ESP_HAL_LOG_LEVEL 3
#define CONFIG_ESP_HAL_EARLY_LOG_LEVEL 3
#define CONFIG_ESP_PLATFORM 1
#define CONFIG_SOC_ADC_SUPPORTED 1
#define CONFIG_SOC_UART_SUPPORTED 1
#define CONFIG_SOC_MCPWM_SUPPORTED 1
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
#define CONFIG_SOC_SDMMC_HOST_SUPPORTED 1
#define CONFIG_SOC_BT_SUPPORTED 1
#define CONFIG_SOC_PCNT_SUPPORTED 1
#define CONFIG_SOC_PHY_SUPPORTED 1
#define CONFIG_SOC_WIFI_SUPPORTED 1
#define CONFIG_SOC_TWAI_SUPPORTED 1
#define CONFIG_SOC_EFUSE_SUPPORTED 1
#define CONFIG_SOC_ULP_SUPPORTED 1
#define CONFIG_SOC_CCOMP_TIMER_SUPPORTED 1
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_TIMER_V1_SUPPORTED 1
#define CONFIG_SOC_I2S_SUPPORTED 1
#define CONFIG_SOC_LCD_I80_SUPPORTED 1
#define CONFIG_SOC_RMT_SUPPORTED 1
#define CONFIG_SOC_SDM_SUPPORTED 1
#define CONFIG_SOC_GPSPI_SUPPORTED 1
#define CONFIG_SOC_LEDC_SUPPORTED 1
#define CONFIG_SOC_I2C_SUPPORTED 1
#define CONFIG_SOC_SUPPORT_COEXISTENCE 1
#define CONFIG_SOC_AES_SUPPORTED 1
#define CONFIG_SOC_MPI_SUPPORTED 1
#define CONFIG_SOC_SHA_SUPPORTED 1
#define CONFIG_SOC_FLASH_ENC_SUPPORTED 1
#define CONFIG_SOC_SECURE_BOOT_SUPPORTED 1
#define CONFIG_SOC_TOUCH_SENSOR_SUPPORTED 1
#define CONFIG_SOC_BOD_SUPPORTED 1
#define CONFIG_SOC_ULP_FSM_SUPPORTED 1
#define CONFIG_SOC_CLK_TREE_SUPPORTED 1
#define CONFIG_SOC_MPU_SUPPORTED 1
#define CONFIG_SOC_WDT_SUPPORTED 1
#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
#define CONFIG_SOC_RNG_SUPPORTED 1
#define CONFIG_SOC_LIGHT_SLEEP_SUPPORTED 1
#define CONFIG_SOC_DEEP_SLEEP_SUPPORTED 1
#define CONFIG_SOC_LP_PERIPH_SHARE_INTERRUPT 1
#define CONFIG_SOC_PM_SUPPORTED 1
#define CONFIG_SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED 1
#define CONFIG_SOC_XTAL_SUPPORT_40M 1
#define CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
#define CONFIG_SOC_ADC_PERIPH_NUM 2
#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 10
#define CONFIG_SOC_ADC_ATTEN_NUM 4
#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 2
#define CONFIG_SOC_ADC_PATT_LEN_MAX 24
#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_SHARED_POWER 1
#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
#define CONFIG_SOC_CPU_CORES_NUM 2
#define CONFIG_SOC_CPU_INTR_NUM 32
#define CONFIG_SOC_CPU_HAS_FPU 1
#define CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES 1
#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 2
#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 2
#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x40
#define CONFIG_SOC_GPIO_PORT 1
#define CONFIG_SOC_GPIO_PIN_COUNT 49
#define CONFIG_SOC_GPIO_VALID_GPIO_MASK 0x1FFFFFFFFFFFF
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 48
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 48
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000
#define CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX 1
#define CONFIG_SOC_GPIO_CLOCKOUT_CHANNEL_NUM 3
#define CONFIG_SOC_I2C_NUM 2
#define CONFIG_SOC_HP_I2C_NUM 2
#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM2PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM2PCM 1
#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 4
#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1
#define CONFIG_SOC_LEDC_TIMER_NUM 4
#define CONFIG_SOC_LEDC_CHANNEL_NUM 8
#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 14
#define CONFIG_SOC_MMU_PERIPH_NUM 1
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1
#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
#define CONFIG_SOC_RTCIO_PIN_COUNT 22
#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1
#define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1
#define CONFIG_SOC_SPI_PERIPH_NUM 3
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI 16
#define CONFIG_SOC_TOUCH_SENSOR_VERSION 2
#define CONFIG_SOC_TOUCH_MIN_CHAN_ID 1
#define CONFIG_SOC_TOUCH_MAX_CHAN_ID 14
#define CONFIG_SOC_TOUCH_SUPPORT_SLEEP_WAKEUP 1
#define CONFIG_SOC_TOUCH_SAMPLE_CFG_NUM 1
#define CONFIG_SOC_TWAI_CONTROLLER_NUM 1
#define CONFIG_SOC_TWAI_MASK_FILTER_NUM 1
#define CONFIG_SOC_UART_NUM 3
#define CONFIG_SOC_UART_HP_NUM 3
#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1
#define CONFIG_SOC_UART_FIFO_LEN 128
#define CONFIG_SOC_UART_BITRATE_MAX 5000000
#define CONFIG_SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE 1
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1
#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA384 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512 1
#define CONFIG_SOC_MPI_MEM_BLOCKS_NUM 4
#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
#define CONFIG_SOC_RSA_MAX_BIT_LEN 4096
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX 64
#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21
#define CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
#define CONFIG_SOC_PM_SUPPORT_MODEM_PD 1
#define CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED 1
#define CONFIG_SOC_PM_MODEM_PD_BY_SW 1
#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1
#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
#define CONFIG_SOC_SDMMC_NUM_SLOTS 2
#define CONFIG_SOC_SDMMC_DATA_WIDTH_MAX 8
#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1
#define CONFIG_SOC_WIFI_CSI_SUPPORT 1
#define CONFIG_SOC_WIFI_MESH_SUPPORT 1
#define CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW 1
#define CONFIG_SOC_BLE_SUPPORTED 1
#define CONFIG_SOC_BLE_MESH_SUPPORTED 1
#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1
#define CONFIG_SOC_BLUFI_SUPPORTED 1
#define CONFIG_SOC_ULP_HAS_ADC 1
#define CONFIG_SOC_PHY_COMBO_MODULE 1
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
#define CONFIG_SOC_RISCV_COPROC_SUPPORTED 1
#define CONFIG_SOC_USB_OTG_SUPPORTED 1
#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
#define CONFIG_SOC_CACHE_SUPPORT_WRAP 1
#define CONFIG_SOC_PSRAM_DMA_CAPABLE 1
#define CONFIG_SOC_XT_WDT_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
#define CONFIG_SOC_HMAC_SUPPORTED 1
#define CONFIG_SOC_DIG_SIGN_SUPPORTED 1
#define CONFIG_SOC_MEMPROT_SUPPORTED 1
#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1
#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1
#define CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED 1
#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 4096
#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
#define CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE 1
#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
#define CONFIG_SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define CONFIG_SOC_SPI_SUPPORT_OCT 1
#define CONFIG_SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1
#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
#define CONFIG_SOC_TOUCH_SUPPORT_BENCHMARK 1
#define CONFIG_SOC_TOUCH_SUPPORT_WATERPROOF 1
#define CONFIG_SOC_TOUCH_SUPPORT_PROX_SENSING 1
#define CONFIG_SOC_TOUCH_SUPPORT_DENOISE_CHAN 1
#define CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM 3
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1
#define CONFIG_SOC_USB_OTG_PERIPH_NUM 1
#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
#define CONFIG_SOC_SHA_SUPPORT_DMA 1
#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_256 1
#define CONFIG_SOC_SHA_SUPPORT_SHA512_T 1
#define CONFIG_SOC_AES_SUPPORT_DMA 1
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
#define CONFIG_SOC_EFUSE_HARD_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_ICACHE 1
#define CONFIG_SOC_EFUSE_XTS_AES_KEY_128 1
#define CONFIG_SOC_EFUSE_XTS_AES_KEY_256 1
#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
#define CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 256
#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
#define CONFIG_SOC_COEX_HW_PTI 1
#define CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE 1
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1
#define CONFIG_SOC_WIFI_HW_TSF 1
#define CONFIG_SOC_WIFI_FTM_SUPPORT 1
#define CONFIG_SOC_GDMA_SUPPORTED 1
#define CONFIG_SOC_UHCI_SUPPORTED 1
#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_CAM_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_I80_LCD_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_RGB_LCD_SUPPORTED 1
#define CONFIG_SOC_LCD_RGB_SUPPORTED 1
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define CONFIG_SOC_SIMD_INSTRUCTION_SUPPORTED 1
#define CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG 1
#define CONFIG_SOC_APB_BACKUP_DMA 1
#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1
#define CONFIG_SOC_CACHE_ACS_INVALID_STATE_ON_PANIC 1
#define CONFIG_SOC_SIMD_PREFERRED_DATA_ALIGNMENT 16
#define CONFIG_SOC_AHB_GDMA_VERSION 1
#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
#define CONFIG_SOC_I2C_SUPPORT_RTC 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
#define CONFIG_SOC_I2S_HW_VERSION_2 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1
#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_DMA 1
#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128
#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 549
#define CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH 128
#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
#define CONFIG_SOC_UHCI_NUM 1
#define CONFIG_SOC_SHA_GDMA 1
#define CONFIG_SOC_AES_GDMA 1
#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
#define CONFIG_SOC_PM_SUPPORT_TAGMEM_PD 1
#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1
#define CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY 1
#define CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL 1
#define CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA 1
#define CONFIG_SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 1
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1
#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING 1
#define CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY 1
#define CONFIG_SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP 1
#define CONFIG_SOC_SPI_MEM_FLASH_SUPPORT_HPM 1
#define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX 1
#define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM 4
#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1
#define CONFIG_SOC_WIFI_TXOP_SUPPORT 1
#define CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND 1
#define CONFIG_SOC_BLE_50_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV 1
#define CONFIG_XTAL_FREQ 40
#define CONFIG_XTAL_FREQ_40 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
#define CONFIG_BOOTLOADER_CPU_CLK_FREQ_MHZ 80
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 240
#define CONFIG_ESP_CLK_FREQ_HZ 240000000
#define CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM 4
#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
#define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1
#define CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL 5
#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1
#define CONFIG_IDF_TARGET_ARCH_XTENSA 1
#define CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM 1
#define CONFIG_ESP_PHY_ENABLED 1
#define CONFIG_portNUM_PROCESSORS 2
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0009
#define CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY 1
#define CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY 1
#define CONFIG_IDF_TARGET_ESP32S3 1
#define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1
#define CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
#define CONFIG_ZEPHYR_HAL_ESPRESSIF_MODULE 1
#define CONFIG_ZEPHYR_HAL_ETHOS_U_MODULE 1
#define CONFIG_ZEPHYR_HAL_GIGADEVICE_MODULE 1
#define CONFIG_ZEPHYR_HAL_INFINEON_MODULE 1
#define CONFIG_ZEPHYR_HAL_INTEL_MODULE 1
#define CONFIG_ZEPHYR_MICROCHIP_MODULE 1
#define CONFIG_ZEPHYR_HAL_NORDIC_MODULE 1
#define CONFIG_ZEPHYR_NUVOTON_MODULE 1
#define CONFIG_ZEPHYR_HAL_NXP_MODULE 1
#define CONFIG_ZEPHYR_OPENISA_MODULE 1
#define CONFIG_ZEPHYR_QUICKLOGIC_MODULE 1
#define CONFIG_ZEPHYR_HAL_REALTEK_MODULE 1
#define CONFIG_ZEPHYR_HAL_RENESAS_MODULE 1
#define CONFIG_ZEPHYR_HAL_RPI_PICO_MODULE 1
#define CONFIG_ZEPHYR_HAL_SIFLI_MODULE 1
#define CONFIG_ZEPHYR_HAL_SILABS_MODULE 1
#define CONFIG_ZEPHYR_HAL_ST_MODULE 1
#define CONFIG_ZEPHYR_HAL_STM32_MODULE 1
#define CONFIG_ZEPHYR_HAL_TDK_MODULE 1
#define CONFIG_ZEPHYR_HAL_TELINK_MODULE 1
#define CONFIG_ZEPHYR_TI_MODULE 1
#define CONFIG_ZEPHYR_HAL_WCH_MODULE 1
#define CONFIG_ZEPHYR_HAL_WURTHELEKTRONIK_MODULE 1
#define CONFIG_ZEPHYR_XTENSA_MODULE 1
#define CONFIG_ZEPHYR_HOSTAP_MODULE 1
#define CONFIG_ZEPHYR_LIBLC3_MODULE 1
#define CONFIG_ZEPHYR_LIBMCTP_MODULE 1
#define CONFIG_ZEPHYR_LIBMETAL_MODULE 1
#define CONFIG_ZEPHYR_LIBSBC_MODULE 1
#define CONFIG_ZEPHYR_LITTLEFS_MODULE 1
#define CONFIG_ZEPHYR_LORA_BASICS_MODEM_MODULE 1
#define CONFIG_ZEPHYR_LORAMAC_NODE_MODULE 1
#define CONFIG_HAS_SEMTECH_RADIO_DRIVERS 1
#define CONFIG_HAS_SEMTECH_SX126X 1
#define CONFIG_ZEPHYR_LVGL_MODULE 1
#define CONFIG_ZEPHYR_MBEDTLS_MODULE 1
#define CONFIG_MBEDTLS_VERSION_4_x 1
#define CONFIG_ZEPHYR_MBEDTLS_3_6_MODULE 1
#define CONFIG_ZEPHYR_MCUBOOT_MODULE 1
#define CONFIG_ZEPHYR_MIPI_SYS_T_MODULE 1
#define CONFIG_ZEPHYR_NANOPB_MODULE 1
#define CONFIG_ZEPHYR_NRF_WIFI_MODULE 1
#define CONFIG_ZEPHYR_OPEN_AMP_MODULE 1
#define CONFIG_ZEPHYR_OPENTHREAD_MODULE 1
#define CONFIG_ZEPHYR_PERCEPIO_MODULE 1
#define CONFIG_ZEPHYR_PICOLIBC_MODULE 1
#define CONFIG_ZEPHYR_PSA_ARCH_TESTS_MODULE 1
#define CONFIG_ZEPHYR_SEGGER_MODULE 1
#define CONFIG_ZEPHYR_TF_M_TESTS_MODULE 1
#define CONFIG_ZEPHYR_TF_PSA_CRYPTO_MODULE 1
#define CONFIG_ZEPHYR_TRUSTED_FIRMWARE_A_MODULE 1
#define CONFIG_ZEPHYR_TRUSTED_FIRMWARE_M_MODULE 1
#define CONFIG_ZEPHYR_UOSCORE_UEDHOC_MODULE 1
#define CONFIG_ZEPHYR_ZCBOR_MODULE 1
#define CONFIG_ZEPHYR_NRF_HW_MODELS_MODULE 1
#define CONFIG_HAS_ESPRESSIF_HAL 1
#define CONFIG_BOARD "xiao_esp32s3"
#define CONFIG_BOARD_REVISION ""
#define CONFIG_BOARD_TARGET "xiao_esp32s3/esp32s3/procpu"
#define CONFIG_BOARD_XIAO_ESP32S3 1
#define CONFIG_BOARD_XIAO_ESP32S3_ESP32S3_PROCPU 1
#define CONFIG_BOARD_QUALIFIERS "esp32s3/procpu"
#define CONFIG_HEAP_MEM_POOL_ADD_SIZE_BOARD 4096
#define CONFIG_SOC "esp32s3"
#define CONFIG_SOC_SERIES "esp32s3"
#define CONFIG_SOC_FAMILY "espressif_esp32"
#define CONFIG_SOC_PART_NUMBER "ESP32S3_WROOM_N8R8"
#define CONFIG_SOC_FAMILY_ESPRESSIF_ESP32 1
#define CONFIG_SOC_SERIES_ESP32S3 1
#define CONFIG_SOC_ESP32S3_WROOM_N8R8 1
#define CONFIG_SOC_ESP32S3 1
#define CONFIG_SOC_ESP32S3_PROCPU 1
#define CONFIG_GPIO_INIT_PRIORITY 40
#define CONFIG_ESP_SIMPLE_BOOT 1
#define CONFIG_ESP32_TIMER_TASK_STACK_SIZE 4096
#define CONFIG_ESP32_TIMER_TASK_PRIO 3
#define CONFIG_ESP_CONSOLE_UART_NUM 4
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 1
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 4
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG 1
#define CONFIG_ESP_CONSOLE 1
#define CONFIG_ESP_USB_SERIAL_JTAG_ENABLED 1
#define CONFIG_ESP32_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT 1
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED 1
#define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP 1
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT 1
#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 1
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE 0x4000
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS 1
#define CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS 8
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B 1
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE 32
#define CONFIG_ESP32S3_DATA_CACHE_32KB 1
#define CONFIG_ESP32S3_DATA_CACHE_SIZE 0x8000
#define CONFIG_ESP32S3_DATA_CACHE_8WAYS 1
#define CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS 8
#define CONFIG_ESP32S3_DATA_CACHE_LINE_32B 1
#define CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE 32
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES 4
#define CONFIG_RESERVE_RTC_MEM 0
#define CONFIG_SOC_LOG_LEVEL_DEFAULT 1
#define CONFIG_SOC_LOG_LEVEL 3
#define CONFIG_ARCH "xtensa"
#define CONFIG_XTENSA 1
#define CONFIG_ARCH_IS_SET 1
#define CONFIG_ARCH_LOG_LEVEL_DEFAULT 1
#define CONFIG_ARCH_LOG_LEVEL 3
#define CONFIG_LITTLE_ENDIAN 1
#define CONFIG_SRAM_SIZE 416
#define CONFIG_SRAM_BASE_ADDRESS 0x3fc88000
#define CONFIG_ARCH_DEVICE_STATE_ALIGN 4
#define CONFIG_SRAM_SW_ISR_TABLE 1
#define CONFIG_EXCEPTION_DEBUG 1
#define CONFIG_ARCH_HAS_TIMING_FUNCTIONS 1
#define CONFIG_ARCH_SUPPORTS_COREDUMP 1
#define CONFIG_ARCH_SUPPORTS_COREDUMP_STACK_PTR 1
#define CONFIG_ARCH_HAS_CODE_DATA_RELOCATION 1
#define CONFIG_CPU_HAS_FPU 1
#define CONFIG_ARCH_HAS_DIRECTED_IPIS 1
#define CONFIG_TOOLCHAIN_HAS_BUILTIN_FFS 1
#define CONFIG_KERNEL_LOG_LEVEL_DEFAULT 1
#define CONFIG_KERNEL_LOG_LEVEL 3
#define CONFIG_NUM_COOP_PRIORITIES 16
#define CONFIG_MAIN_THREAD_PRIORITY 0
#define CONFIG_COOP_ENABLED 1
#define CONFIG_PREEMPT_ENABLED 1
#define CONFIG_PRIORITY_CEILING -128
#define CONFIG_THREAD_STACK_INFO 1
#define CONFIG_SCHED_SIMPLE 1
#define CONFIG_WAITQ_SIMPLE 1
#define CONFIG_ERRNO 1
#define CONFIG_BOOT_BANNER 1
#define CONFIG_BOOT_BANNER_STRING "Booting Zephyr OS build"
#define CONFIG_BOOT_DELAY 0
#define CONFIG_SYSTEM_WORKQUEUE_PRIORITY -1
#define CONFIG_SYSTEM_WORKQUEUE_WORK_TIMEOUT_MS 0
#define CONFIG_ATOMIC_OPERATIONS_BUILTIN 1
#define CONFIG_TIMESLICING 1
#define CONFIG_TIMESLICE_PRIORITY 0
#define CONFIG_POLL 1
#define CONFIG_NUM_MBOX_ASYNC_MSGS 10
#define CONFIG_HEAP_MEM_POOL_SIZE 4096
#define CONFIG_TIMEOUT_64BIT 1
#define CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS 365
#define CONFIG_USE_SWITCH 1
#define CONFIG_USE_SWITCH_SUPPORTED 1
#define CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE 1
#define CONFIG_TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU 1
#define CONFIG_KERNEL_INIT_PRIORITY_OBJECTS 30
#define CONFIG_KERNEL_INIT_PRIORITY_LIBC 35
#define CONFIG_KERNEL_INIT_PRIORITY_DEFAULT 40
#define CONFIG_KERNEL_INIT_PRIORITY_DEVICE 50
#define CONFIG_APPLICATION_INIT_PRIORITY 90
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL_DEFAULT 1
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL 3
#define CONFIG_CLOCK_CONTROL_ESP32 1
#define CONFIG_CLOCK_CONTROL_ESP32_RTC_CLK_SRC_INT_RC 1
#define CONFIG_CLOCK_CONTROL_ESP32_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_CLOCK_CONTROL_TISCI_PRIORITY 40
#define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128
#define CONFIG_CONSOLE_HAS_DRIVER 1
#define CONFIG_CONSOLE_INIT_PRIORITY 60
#define CONFIG_UART_CONSOLE 1
#define CONFIG_UART_CONSOLE_LOG_LEVEL_DEFAULT 1
#define CONFIG_UART_CONSOLE_LOG_LEVEL 3
#define CONFIG_GPIO_LOG_LEVEL_DEFAULT 1
#define CONFIG_GPIO_LOG_LEVEL 3
#define CONFIG_GPIO_ESP32 1
#define CONFIG_INTC_INIT_PRIORITY 40
#define CONFIG_INTC_LOG_LEVEL_DEFAULT 1
#define CONFIG_INTC_LOG_LEVEL 3
#define CONFIG_INTC_ESP32 1
#define CONFIG_LORA 1
#define CONFIG_LORA_MODULE_BACKEND_LORAMAC_NODE 1
#define CONFIG_LORA_LOG_LEVEL_DEFAULT 1
#define CONFIG_LORA_LOG_LEVEL 3
#define CONFIG_LORA_INIT_PRIORITY 90
#define CONFIG_LORA_SX126X 1
#define CONFIG_PINCTRL 1
#define CONFIG_PINCTRL_LOG_LEVEL_DEFAULT 1
#define CONFIG_PINCTRL_LOG_LEVEL 3
#define CONFIG_PINCTRL_ESP32 1
#define CONFIG_SERIAL_HAS_DRIVER 1
#define CONFIG_SERIAL_SUPPORT_ASYNC 1
#define CONFIG_SERIAL_SUPPORT_INTERRUPT 1
#define CONFIG_SERIAL_INIT_PRIORITY 50
#define CONFIG_UART_LOG_LEVEL_DEFAULT 1
#define CONFIG_UART_LOG_LEVEL 3
#define CONFIG_UART_ESP32 1
#define CONFIG_SERIAL_ESP32_USB 1
#define CONFIG_UART_ESP32_TX_FIFO_THRESH 0x1
#define CONFIG_UART_ESP32_RX_FIFO_THRESH 0x16
#define CONFIG_SPI_INIT_PRIORITY 50
#define CONFIG_SPI_COMPLETION_TIMEOUT_TOLERANCE 200
#define CONFIG_SPI_LOG_LEVEL_DEFAULT 1
#define CONFIG_SPI_LOG_LEVEL 3
#define CONFIG_ESP32_SPIM 1
#define CONFIG_SYSTEM_CLOCK_INIT_PRIORITY 0
#define CONFIG_TICKLESS_CAPABLE 1
#define CONFIG_XTENSA_TIMER_LPM_TIMER_NONE 1
#define CONFIG_FULL_LIBC_SUPPORTED 1
#define CONFIG_MINIMAL_LIBC_SUPPORTED 1
#define CONFIG_PICOLIBC_SUPPORTED 1
#define CONFIG_PICOLIBC 1
#define CONFIG_COMMON_LIBC_ABORT 1
#define CONFIG_COMMON_LIBC_TIME 1
#define CONFIG_COMMON_LIBC_MALLOC 1
#define CONFIG_COMMON_LIBC_CALLOC 1
#define CONFIG_COMMON_LIBC_REALLOCARRAY 1
#define CONFIG_PICOLIBC_USE_TOOLCHAIN 1
#define CONFIG_PICOLIBC_IO_LONG_LONG 1
#define CONFIG_STDOUT_CONSOLE 1
#define CONFIG_NEED_LIBC_MEM_PARTITION 1
#define CONFIG_SYS_HEAP_ALLOC_LOOPS 3
#define CONFIG_SYS_HEAP_ARRAY_SIZE 0
#define CONFIG_SYS_HEAP_HARDENING_BASIC 1
#define CONFIG_SYS_HEAP_HARDENING_LEVEL 1
#define CONFIG_SYS_HEAP_LOG_LEVEL_DEFAULT 1
#define CONFIG_SYS_HEAP_LOG_LEVEL 3
#define CONFIG_SYS_HEAP_AUTO 1
#define CONFIG_MPSC_PBUF 1
#define CONFIG_HAS_POWEROFF 1
#define CONFIG_CBPRINTF_COMPLETE 1
#define CONFIG_CBPRINTF_FULL_INTEGRAL 1
#define CONFIG_CBPRINTF_PACKAGE_LOG_LEVEL_DEFAULT 1
#define CONFIG_CBPRINTF_PACKAGE_LOG_LEVEL 3
#define CONFIG_CBPRINTF_CONVERT_CHECK_PTR 1
#define CONFIG_CPU_LOAD_LOG_LEVEL_DEFAULT 1
#define CONFIG_CPU_LOAD_LOG_LEVEL 3
#define CONFIG_POSIX_AEP_CHOICE_ZEPHYR 1
#define CONFIG_TC_PROVIDES_POSIX_C_LANG_SUPPORT_R 1
#define CONFIG_POSIX_C_LANG_SUPPORT_R 1
#define CONFIG_POSIX_C_LIB_EXT 1
#define CONFIG_LIBGCC_RTLIB 1
#define CONFIG_RING_BUFFER 1
#define CONFIG_GETOPT 1
#define CONFIG_TIMEUTIL_APPLY_SKEW 1
#define CONFIG_PRINTK 1
#define CONFIG_EARLY_CONSOLE 1
#define CONFIG_ASSERT_VERBOSE 1
#define CONFIG_CPU_LOAD_LOG_PERIODICALLY 0
#define CONFIG_LOG_CORE_INIT_PRIORITY 0
#define CONFIG_LOG_MODE_DEFERRED 1
#define CONFIG_LOG_FLUSH_SLEEP_US 10000
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_OVERRIDE_LEVEL 0
#define CONFIG_LOG_MAX_LEVEL 4
#define CONFIG_LOG_PRINTK 1
#define CONFIG_LOG_MODE_OVERFLOW 1
#define CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD 10
#define CONFIG_LOG_PROCESS_THREAD 1
#define CONFIG_LOG_PROCESS_THREAD_STARTUP_DELAY_MS 0
#define CONFIG_LOG_PROCESS_THREAD_SLEEP_MS 1000
#define CONFIG_LOG_BUFFER_SIZE 1024
#define CONFIG_LOG_TRACE_SHORT_TIMESTAMP 1
#define CONFIG_LOG_FUNC_NAME_PREFIX_DBG 1
#define CONFIG_LOG_BACKEND_SHOW_TIMESTAMP 1
#define CONFIG_LOG_BACKEND_SHOW_LEVEL 1
#define CONFIG_LOG_BACKEND_SHOW_COLOR 1
#define CONFIG_LOG_TAG_MAX_LEN 0
#define CONFIG_LOG_BACKEND_SUPPORTS_FORMAT_TIMESTAMP 1
#define CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP 1
#define CONFIG_LOG_OUTPUT_FORMAT_TIME_TIMESTAMP 1
#define CONFIG_LOG_BACKEND_UART 1
#define CONFIG_LOG_BACKEND_UART_BUFFER_SIZE 1
#define CONFIG_LOG_BACKEND_UART_AUTOSTART 1
#define CONFIG_LOG_BACKEND_UART_OUTPUT_TEXT 1
#define CONFIG_LOG_BACKEND_UART_OUTPUT_DEFAULT 0
#define CONFIG_LOG_USE_VLA 1
#define CONFIG_LOG_SIMPLE_MSG_OPTIMIZE 1
#define CONFIG_LOG_FAILURE_REPORT_PERIOD 1000
#define CONFIG_LOG_RATELIMIT 1
#define CONFIG_LOG_RATELIMIT_INTERVAL_MS 5000
#define CONFIG_LOG_OUTPUT 1
#define CONFIG_HAS_PM 1
#define CONFIG_TIMER_RANDOM_INITIAL_STATE 123456789
#define CONFIG_ENTROPY_NODE_ENABLED 1
#define CONFIG_COVERAGE_DUMP_PATH_EXCLUDE ""
#define CONFIG_TOOLCHAIN_ZEPHYR_1_0 1
#define CONFIG_TOOLCHAIN_ZEPHYR_SUPPORTS_THREAD_LOCAL_STORAGE 1
#define CONFIG_TOOLCHAIN_ZEPHYR_SUPPORTS_GNU_EXTENSIONS 1
#define CONFIG_PICOLIBC_DEFAULT 1
#define CONFIG_LINKER_ORPHAN_SECTION_WARN 1
#define CONFIG_FLASH_LOAD_SIZE 0x0
#define CONFIG_ROM_END_OFFSET 0x0
#define CONFIG_LD_LINKER_SCRIPT_SUPPORTED 1
#define CONFIG_LD_LINKER_TEMPLATE 1
#define CONFIG_LINKER_SORT_BY_ALIGNMENT 1
#define CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT 1
#define CONFIG_LINKER_ITERABLE_SUBALIGN 4
#define CONFIG_STD_C17 1
#define CONFIG_TOOLCHAIN_SUPPORTS_GNU_EXTENSIONS 1
#define CONFIG_SIZE_OPTIMIZATIONS 1
#define CONFIG_COMPILER_TRACK_MACRO_EXPANSION 1
#define CONFIG_COMPILER_COLOR_DIAGNOSTICS 1
#define CONFIG_FORTIFY_SOURCE_COMPILE_TIME 1
#define CONFIG_COMPILER_OPT ""
#define CONFIG_TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS 1
#define CONFIG_TOOLCHAIN_SUPPORTS_VARIABLE_CLEANUP_ATTRIBUTE 1
#define CONFIG_COMPILER_CODEGEN_VLIW_AUTO 1
#define CONFIG_RUNTIME_ERROR_CHECKS 1
#define CONFIG_KERNEL_BIN_NAME "zephyr"
#define CONFIG_OUTPUT_STAT 1
#define CONFIG_OUTPUT_PRINT_MEMORY_USAGE 1
#define CONFIG_BUILD_GAP_FILL_PATTERN 0xFF
#define CONFIG_BUILD_OUTPUT_STRIP_PATHS 1
#define CONFIG_CHECK_INIT_PRIORITIES 1
#define CONFIG_WARN_DEPRECATED 1
#define CONFIG_ENFORCE_ZEPHYR_STDINT 1
#define CONFIG_LEGACY_GENERATED_INCLUDE_PATH 1
#define CONFIG_LORAMODEM_KISS_IFACE_UART 1
#define CONFIG_LORAMODEM_LORA_FREQ_HZ 869618000
#define CONFIG_LORAMODEM_LORA_SF 8
#define CONFIG_LORAMODEM_LORA_BW 62
#define CONFIG_LORAMODEM_LORA_CR 5
#define CONFIG_LORAMODEM_LORA_TX_POWER_DBM 21
#define CONFIG_LORAMODEM_LORA_PREAMBLE_LEN 8
#define CONFIG_LORAMODEM_MAX_PACKET_SIZE 255
