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maze
2026-03-25 18:14:45 +01:00
commit d074cd2e43
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6
boards/heltec/heltec_meshpocket/Kconfig.defconfig Normal file
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if BOARD_HELTEC_MESHPOCKET
config BOARD
default "heltec_meshpocket"
endif # BOARD_HELTEC_MESHPOCKET

2
boards/heltec/heltec_meshpocket/Kconfig.heltec_meshpocket Normal file
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config BOARD_HELTEC_MESHPOCKET
select SOC_NRF52840_QIAA

2
boards/heltec/heltec_meshpocket/board.cmake Normal file
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# Heltec MeshPocket — board.cmake
include(${ZEPHYR_BASE}/boards/nordic/common/board.cmake)

7
boards/heltec/heltec_meshpocket/board.yml Normal file
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board:
name: heltec_meshpocket
full_name: "Heltec MeshPocket"
vendor: heltec
url: https://heltec.org/project/mesh-pocket/
socs:
- name: nrf52840

47
boards/heltec/heltec_meshpocket/heltec_meshpocket-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec MeshPocket — pin control definitions
* SoC: nRF52840-QIAA
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 8)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 6)>,
<NRF_PSEL(UART_RX, 0, 8)>;
low-power-enable;
};
};
/* SPI1 for SX1262 */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 26)>,
<NRF_PSEL(SPIM_MOSI, 0, 27)>,
<NRF_PSEL(SPIM_MISO, 0, 28)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 26)>,
<NRF_PSEL(SPIM_MOSI, 0, 27)>,
<NRF_PSEL(SPIM_MISO, 0, 28)>;
low-power-enable;
};
};
};

96
boards/heltec/heltec_meshpocket/heltec_meshpocket.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec MeshPocket — Device Tree Source
* SoC: nRF52840-QIAA
* Radio: SX1262 (crystal oscillator, no TCXO)
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "heltec_meshpocket-pinctrl.dtsi"
/ {
model = "Heltec MeshPocket";
compatible = "heltec,meshpocket";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

7
boards/heltec/heltec_meshpocket/heltec_meshpocket_defconfig Normal file
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CONFIG_SOC_SERIES_NRF52X=y
CONFIG_BOARD_HELTEC_MESHPOCKET=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_UART_CONSOLE=y
CONFIG_SPI=y
CONFIG_GPIO=y

6
boards/heltec/heltec_t114/Kconfig.defconfig Normal file
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if BOARD_HELTEC_T114
config BOARD
default "heltec_t114"
endif # BOARD_HELTEC_T114

2
boards/heltec/heltec_t114/Kconfig.heltec_t114 Normal file
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config BOARD_HELTEC_T114
select SOC_NRF52840_QIAA

7
boards/heltec/heltec_t114/board.cmake Normal file
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# Heltec T114 — board.cmake
# Uses nrfjprog or pyocd for flashing via SWD.
# The board exposes a SWD header for programming.
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(pyocd "--target=nrf52840")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

7
boards/heltec/heltec_t114/board.yml Normal file
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board:
name: heltec_t114
full_name: "Heltec Mesh Node T114"
vendor: heltec
url: https://heltec.org/project/mesh-node-t114/
socs:
- name: nrf52840

46
boards/heltec/heltec_t114/heltec_t114-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec T114 — pin control definitions
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 10)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 9)>;
bias-pull-up;
};
};
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 10)>,
<NRF_PSEL(UART_RX, 0, 9)>;
low-power-enable;
};
};
/* SPI1 for LR1110 */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
<NRF_PSEL(SPIM_MOSI, 0, 22)>,
<NRF_PSEL(SPIM_MISO, 0, 23)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
<NRF_PSEL(SPIM_MOSI, 0, 22)>,
<NRF_PSEL(SPIM_MISO, 0, 23)>;
low-power-enable;
};
};
};

115
boards/heltec/heltec_t114/heltec_t114.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec Mesh Node T114 — Device Tree Source
* SoC: nRF52840 QIAAVariant
* Radio: SX1262
*
* NOTE: GPIO pin numbers are placeholders. Verify against the T114
* schematic/documentation before using with real hardware.
* The T114 uses the nRF52840 SoC in a similar form factor to the
* RAK4631, but with different GPIO assignments.
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "heltec_t114-pinctrl.dtsi"
/ {
model = "Heltec Mesh Node T114";
compatible = "heltec,mesh-node-t114";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
led0 = &led0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
/* TODO: verify LED GPIO from T114 schematic */
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
label = "LED 0";
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart1 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
};
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
tcxo-power-startup-delay-ms = <5>;
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

8
boards/heltec/heltec_t114/heltec_t114_defconfig Normal file
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CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_HELTEC_T114=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_NRFX_POWER=y

6
boards/heltec/heltec_wifi_lora32_v3/Kconfig.defconfig Normal file
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if BOARD_HELTEC_WIFI_LORA32_V3
config BOARD
default "heltec_wifi_lora32_v3"
endif # BOARD_HELTEC_WIFI_LORA32_V3

3
boards/heltec/heltec_wifi_lora32_v3/Kconfig.heltec_wifi_lora32_v3 Normal file
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config BOARD_HELTEC_WIFI_LORA32_V3
select SOC_ESP32S3_PROCPU if BOARD_HELTEC_WIFI_LORA32_V3_PROCPU
select SOC_ESP32S3_APPCPU if BOARD_HELTEC_WIFI_LORA32_V3_APPCPU

3
boards/heltec/heltec_wifi_lora32_v3/board.cmake Normal file
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# Heltec WiFi LoRa 32 V3 — board.cmake
# Uses esptool for flashing over CP2102 USB-UART bridge
include(${ZEPHYR_BASE}/boards/espressif/common/board.cmake)

10
boards/heltec/heltec_wifi_lora32_v3/board.yml Normal file
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board:
name: heltec_wifi_lora32_v3
full_name: "Heltec WiFi LoRa 32 V3"
vendor: heltec
url: https://heltec.org/project/wifi-lora-32-v3/
socs:
- name: esp32s3
variants:
- name: procpu
- name: appcpu

34
boards/heltec/heltec_wifi_lora32_v3/heltec_wifi_lora32_v3-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec WiFi LoRa 32 V3 — pin control definitions
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO43>;
output-enable;
};
group2 {
pinmux = <UART0_RX_GPIO44>;
bias-pull-up;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO11>,
<SPIM2_SCLK_GPIO9>,
<SPIM2_CSEL_GPIO8>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO10>;
output-enable;
};
};
};

109
boards/heltec/heltec_wifi_lora32_v3/heltec_wifi_lora32_v3_procpu.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec WiFi LoRa 32 V3 — Device Tree Source (PROCPU)
*
* SoC: ESP32-S3
* Radio: SX1262
* Console: UART0 via CP2102 USB-UART bridge (GPIO43=TX, GPIO44=RX)
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_fn8r2.dtsi>
#include "heltec_wifi_lora32_v3-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Heltec WiFi LoRa 32 V3 PROCPU";
compatible = "heltec,wifi-lora-32-v3";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash-controller = &flash;
};
aliases {
lora0 = &lora;
led0 = &led_white;
};
leds {
compatible = "gpio-leds";
led_white: led_0 {
gpios = <&gpio0 35 GPIO_ACTIVE_HIGH>;
label = "White LED";
};
};
buttons {
compatible = "gpio-keys";
boot_button: button_0 {
gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Boot Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&spi2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <4000000>;
reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
tcxo-power-startup-delay-ms = <5>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00300000>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 0x00300000>;
};
storage_partition: partition@610000 {
label = "storage";
reg = <0x00610000 0x001f0000>;
};
};
};

7
boards/heltec/heltec_wifi_lora32_v3/heltec_wifi_lora32_v3_procpu_defconfig Normal file
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CONFIG_SOC_SERIES_ESP32S3=y
CONFIG_BOARD_HELTEC_WIFI_LORA32_V3=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_UART_CONSOLE=y
CONFIG_SPI=y
CONFIG_GPIO=y

6
boards/heltec/heltec_wifi_lora32_v4/Kconfig.defconfig Normal file
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if BOARD_HELTEC_WIFI_LORA32_V4
config BOARD
default "heltec_wifi_lora32_v4"
endif # BOARD_HELTEC_WIFI_LORA32_V4

3
boards/heltec/heltec_wifi_lora32_v4/Kconfig.heltec_wifi_lora32_v4 Normal file
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config BOARD_HELTEC_WIFI_LORA32_V4
select SOC_ESP32S3_PROCPU if BOARD_HELTEC_WIFI_LORA32_V4_PROCPU
select SOC_ESP32S3_APPCPU if BOARD_HELTEC_WIFI_LORA32_V4_APPCPU

3
boards/heltec/heltec_wifi_lora32_v4/board.cmake Normal file
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# Heltec WiFi LoRa 32 V4 — board.cmake
# Uses esptool for flashing over USB-C (direct ESP32-S3 USB)
include(${ZEPHYR_BASE}/boards/espressif/common/board.cmake)

10
boards/heltec/heltec_wifi_lora32_v4/board.yml Normal file
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board:
name: heltec_wifi_lora32_v4
full_name: "Heltec WiFi LoRa 32 V4"
vendor: heltec
url: https://heltec.org/project/wifi-lora-32-v4/
socs:
- name: esp32s3
variants:
- name: procpu
- name: appcpu

23
boards/heltec/heltec_wifi_lora32_v4/heltec_wifi_lora32_v4-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec WiFi LoRa 32 V4 — pin control definitions
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
&pinctrl {
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO11>,
<SPIM2_SCLK_GPIO9>,
<SPIM2_CSEL_GPIO8>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO10>;
output-enable;
};
};
};

111
boards/heltec/heltec_wifi_lora32_v4/heltec_wifi_lora32_v4_procpu.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Heltec WiFi LoRa 32 V4 — Device Tree Source (PROCPU)
*
* Based on Heltec WiFi LoRa 32 V3 with the following differences:
* - No CP2102 USB-UART bridge; direct ESP32-S3 USB-C
* - Console routed to usb_serial instead of uart0
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_fn8r2.dtsi>
#include "heltec_wifi_lora32_v4-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Heltec WiFi LoRa 32 V4 PROCPU";
compatible = "heltec,wifi-lora-32-v4";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash-controller = &flash;
};
aliases {
lora0 = &lora;
led0 = &led_white;
};
leds {
compatible = "gpio-leds";
led_white: led_0 {
/* V4 LED pin — verify from schematic */
gpios = <&gpio0 35 GPIO_ACTIVE_HIGH>;
label = "White LED";
};
};
buttons {
compatible = "gpio-keys";
boot_button: button_0 {
gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Boot Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&usb_serial {
status = "okay";
};
&uart0 {
status = "disabled";
};
&spi2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <4000000>;
reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
tcxo-power-startup-delay-ms = <5>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00300000>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 0x00300000>;
};
storage_partition: partition@610000 {
label = "storage";
reg = <0x00610000 0x001f0000>;
};
};
};

7
boards/heltec/heltec_wifi_lora32_v4/heltec_wifi_lora32_v4_procpu_defconfig Normal file
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CONFIG_SOC_SERIES_ESP32S3=y
CONFIG_BOARD_HELTEC_WIFI_LORA32_V4=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_UART_CONSOLE=y
CONFIG_SPI=y
CONFIG_GPIO=y

10
boards/heltec_t114.conf Normal file
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# Heltec T114 (Mesh Node T114) — nRF52840 + SX1262
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

17
boards/heltec_t114.overlay Normal file
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@@ -0,0 +1,17 @@
/*
* Heltec T114 (Mesh Node T114) — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI1 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

7
boards/heltec_wifi_lora32_v2.conf Normal file
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@@ -0,0 +1,7 @@
# Heltec WiFi LoRa 32 V2 — ESP32 + SX1276
# Uses hardware UART over CP2102 USB-Serial bridge
CONFIG_LORAMODEM_KISS_IFACE_UART=y
# SX1276 driver (via loramac-node)
CONFIG_LORA_SX12XX=y

11
boards/heltec_wifi_lora32_v2.overlay Normal file
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@@ -0,0 +1,11 @@
/*
* Heltec WiFi LoRa 32 V2 — application DTS overlay
* KISS interface: UART0 (via CP2102 USB-Serial bridge)
* LoRa: SX1276 on SPI2 (already defined in upstream board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &uart0;
};
};

10
boards/heltec_wifi_lora32_v3_procpu.conf Normal file
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@@ -0,0 +1,10 @@
# Heltec WiFi LoRa 32 V3 (procpu) — ESP32-S3 + SX1262
# Uses USB CDC-ACM (direct ESP32-S3 USB, no CP2102)
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

17
boards/heltec_wifi_lora32_v3_procpu.overlay Normal file
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@@ -0,0 +1,17 @@
/*
* Heltec WiFi LoRa 32 V3 (procpu) — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI2 (already defined in upstream board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

10
boards/heltec_wifi_lora32_v4_procpu.conf Normal file
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@@ -0,0 +1,10 @@
# Heltec WiFi LoRa 32 V4 (procpu) — ESP32-S3 + SX1262
# Uses USB CDC-ACM (direct USB-C, no CP2102)
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

17
boards/heltec_wifi_lora32_v4_procpu.overlay Normal file
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@@ -0,0 +1,17 @@
/*
* Heltec WiFi LoRa 32 V4 (procpu) — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI2 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

6
boards/lilygo/lilygo_tbeam/Kconfig.defconfig Normal file
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@@ -0,0 +1,6 @@
if BOARD_LILYGO_TBEAM
config BOARD
default "lilygo_tbeam"
endif # BOARD_LILYGO_TBEAM

3
boards/lilygo/lilygo_tbeam/Kconfig.lilygo_tbeam Normal file
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@@ -0,0 +1,3 @@
config BOARD_LILYGO_TBEAM
select SOC_ESP32_PROCPU if BOARD_LILYGO_TBEAM_PROCPU
select SOC_ESP32_APPCPU if BOARD_LILYGO_TBEAM_APPCPU

3
boards/lilygo/lilygo_tbeam/board.cmake Normal file
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@@ -0,0 +1,3 @@
# LilyGo T-Beam — board.cmake
# Uses esptool for flashing over USB-to-serial (CP2104)
include(${ZEPHYR_BASE}/boards/espressif/common/board.cmake)

10
boards/lilygo/lilygo_tbeam/board.yml Normal file
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@@ -0,0 +1,10 @@
board:
name: lilygo_tbeam
full_name: "LilyGo T-Beam"
vendor: lilygo
url: https://www.lilygo.cc/products/t-beam-v1-1
socs:
- name: esp32
variants:
- name: procpu
- name: appcpu

36
boards/lilygo/lilygo_tbeam/lilygo_tbeam-pinctrl.dtsi Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* LilyGo T-Beam V1.1 — pin control definitions
* SoC: ESP32-D0WD
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO1>;
output-enable;
};
group2 {
pinmux = <UART0_RX_GPIO3>;
bias-pull-up;
};
};
/* SPI3 (VSPI) for SX1276/SX1278 */
spim3_default: spim3_default {
group1 {
pinmux = <SPIM3_MISO_GPIO19>,
<SPIM3_SCLK_GPIO5>,
<SPIM3_CSEL_GPIO18>;
};
group2 {
pinmux = <SPIM3_MOSI_GPIO27>;
output-enable;
};
};
};

102
boards/lilygo/lilygo_tbeam/lilygo_tbeam_procpu.dts Normal file
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@@ -0,0 +1,102 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* LilyGo T-Beam V1.1 — Device Tree Source (PROCPU)
*
* SoC: ESP32-D0WD
* Radio: SX1276 / SX1278 (LORA32 module)
* Flash: 4 MB
*
* LoRa: MOSI=27 MISO=19 SCK=5 NSS=18 RST=23 DIO0=26
* UART0: TX=1 RX=3 (via CP2104 USB-serial)
*/
/dts-v1/;
#include <espressif/esp32/esp32_d0wd_v3.dtsi>
#include "lilygo_tbeam-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "LilyGo T-Beam V1.1 PROCPU";
compatible = "lilygo,t-beam";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash-controller = &flash;
};
aliases {
lora0 = &lora;
};
buttons {
compatible = "gpio-keys";
boot_button: button_0 {
gpios = <&gpio0 38 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Boot Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&spi3 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spim3_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1276";
reg = <0>;
spi-max-frequency = <8000000>;
reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
dio1-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
power-amplifier-output = "pa-boost";
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00180000>;
};
slot1_partition: partition@190000 {
label = "image-1";
reg = <0x00190000 0x00180000>;
};
storage_partition: partition@310000 {
label = "storage";
reg = <0x00310000 0x000F0000>;
};
};
};

7
boards/lilygo/lilygo_tbeam/lilygo_tbeam_procpu_defconfig Normal file
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@@ -0,0 +1,7 @@
CONFIG_SOC_SERIES_ESP32=y
CONFIG_BOARD_LILYGO_TBEAM=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_UART_CONSOLE=y
CONFIG_SPI=y
CONFIG_GPIO=y

6
boards/rak/rak_wismesh_pocket/Kconfig.defconfig Normal file
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@@ -0,0 +1,6 @@
if BOARD_RAK_WISMESH_POCKET
config BOARD
default "rak_wismesh_pocket"
endif # BOARD_RAK_WISMESH_POCKET

2
boards/rak/rak_wismesh_pocket/Kconfig.rak_wismesh_pocket Normal file
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@@ -0,0 +1,2 @@
config BOARD_RAK_WISMESH_POCKET
select SOC_NRF52840_QIAA

9
boards/rak/rak_wismesh_pocket/board.cmake Normal file
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@@ -0,0 +1,9 @@
# RAK WisMesh Pocket — board.cmake
# Uses nrfjprog or pyocd for flashing via SWD.
# J-Link is the recommended debugger for RAK WisBlock-family boards.
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000" "--reset-after-load")
board_runner_args(pyocd "--target=nrf52840")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

7
boards/rak/rak_wismesh_pocket/board.yml Normal file
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@@ -0,0 +1,7 @@
board:
name: rak_wismesh_pocket
full_name: "RAK WisMesh Pocket"
vendor: rak
url: https://docs.rakwireless.com/Product-Categories/WisMesh/
socs:
- name: nrf52840

47
boards/rak/rak_wismesh_pocket/rak_wismesh_pocket-pinctrl.dtsi Normal file
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@@ -0,0 +1,47 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* RAK WisMesh Pocket — pin control definitions
* Matches RAK4631 GPIO assignments. Verify from WisMesh Pocket schematic.
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 19)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 18)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 19)>,
<NRF_PSEL(UART_RX, 0, 18)>;
low-power-enable;
};
};
/* SPI1 for SX1262 — RAK4631 pin assignments */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 3)>,
<NRF_PSEL(SPIM_MOSI, 1, 2)>,
<NRF_PSEL(SPIM_MISO, 1, 1)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 3)>,
<NRF_PSEL(SPIM_MOSI, 1, 2)>,
<NRF_PSEL(SPIM_MISO, 1, 1)>;
low-power-enable;
};
};
};

119
boards/rak/rak_wismesh_pocket/rak_wismesh_pocket_nrf52840.dts Normal file
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@@ -0,0 +1,119 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* RAK WisMesh Pocket — Device Tree Source
* SoC: nRF52840 (same as RAK4631 WisBlock Core)
* Radio: SX1262
*
* The WisMesh Pocket is derived from the RAK4631 with a different
* form factor optimized for portable deployment. GPIO assignments
* are assumed identical to RAK4631; verify against the WisMesh
* Pocket schematic before using with real hardware.
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "rak_wismesh_pocket-pinctrl.dtsi"
/ {
model = "RAK WisMesh Pocket";
compatible = "rak,wismesh-pocket";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
led0 = &led_green;
};
leds {
compatible = "gpio-leds";
led_green: led_0 {
/* RAK4631 green LED — verify for WisMesh Pocket */
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
label = "Green LED";
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
/*
* SX1262 on SPI1
* GPIO assignments match RAK4631 — verify for WisMesh Pocket.
*/
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
tcxo-power-startup-delay-ms = <5>;
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

8
boards/rak/rak_wismesh_pocket/rak_wismesh_pocket_nrf52840_defconfig Normal file
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@@ -0,0 +1,8 @@
CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_RAK_WISMESH_POCKET=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_NRFX_POWER=y

6
boards/rak/rak_wismesh_tag/Kconfig.defconfig Normal file
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@@ -0,0 +1,6 @@
if BOARD_RAK_WISMESH_TAG
config BOARD
default "rak_wismesh_tag"
endif # BOARD_RAK_WISMESH_TAG

2
boards/rak/rak_wismesh_tag/Kconfig.rak_wismesh_tag Normal file
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@@ -0,0 +1,2 @@
config BOARD_RAK_WISMESH_TAG
select SOC_NRF52840_QIAA

9
boards/rak/rak_wismesh_tag/board.cmake Normal file
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@@ -0,0 +1,9 @@
# RAK WisMesh Tag — board.cmake
# Uses nrfjprog or pyocd for flashing via SWD.
# J-Link is the recommended debugger for RAK WisBlock-family boards.
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000" "--reset-after-load")
board_runner_args(pyocd "--target=nrf52840")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

7
boards/rak/rak_wismesh_tag/board.yml Normal file
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@@ -0,0 +1,7 @@
board:
name: rak_wismesh_tag
full_name: "RAK WisMesh Tag"
vendor: rak
url: https://docs.rakwireless.com/Product-Categories/WisMesh/
socs:
- name: nrf52840

47
boards/rak/rak_wismesh_tag/rak_wismesh_tag-pinctrl.dtsi Normal file
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@@ -0,0 +1,47 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* RAK WisMesh Tag — pin control definitions
* Matches RAK4631 GPIO assignments. Verify from WisMesh Tag schematic.
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 19)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 18)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 19)>,
<NRF_PSEL(UART_RX, 0, 18)>;
low-power-enable;
};
};
/* SPI1 for SX1262 — RAK4631 pin assignments */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 3)>,
<NRF_PSEL(SPIM_MOSI, 1, 2)>,
<NRF_PSEL(SPIM_MISO, 1, 1)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 3)>,
<NRF_PSEL(SPIM_MOSI, 1, 2)>,
<NRF_PSEL(SPIM_MISO, 1, 1)>;
low-power-enable;
};
};
};

119
boards/rak/rak_wismesh_tag/rak_wismesh_tag_nrf52840.dts Normal file
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@@ -0,0 +1,119 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* RAK WisMesh Tag — Device Tree Source
* SoC: nRF52840 (same as RAK4631 WisBlock Core)
* Radio: SX1262
*
* The WisMesh Tag is derived from the RAK4631 with a different
* form factor. GPIO assignments are assumed identical to RAK4631;
* verify against the WisMesh Tag schematic before using with
* real hardware.
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "rak_wismesh_tag-pinctrl.dtsi"
/ {
model = "RAK WisMesh Tag";
compatible = "rak,wismesh-tag";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
led0 = &led_green;
};
leds {
compatible = "gpio-leds";
led_green: led_0 {
/* RAK4631 green LED — verify for WisMesh Tag */
gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
label = "Green LED";
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
/*
* SX1262 on SPI1
* GPIO assignments match RAK4631 — verify for WisMesh Tag.
*/
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1262";
reg = <0>;
spi-max-frequency = <1000000>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
dio1-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
dio2-tx-enable;
dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
tcxo-power-startup-delay-ms = <5>;
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

8
boards/rak/rak_wismesh_tag/rak_wismesh_tag_nrf52840_defconfig Normal file
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@@ -0,0 +1,8 @@
CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_RAK_WISMESH_TAG=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_NRFX_POWER=y

10
boards/rak4631_nrf52840.conf Normal file
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@@ -0,0 +1,10 @@
# RAK WisBlock (RAK4631) — nRF52840 + SX1262
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

17
boards/rak4631_nrf52840.overlay Normal file
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@@ -0,0 +1,17 @@
/*
* RAK WisBlock (RAK4631 / nRF52840) — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI1 (already defined in upstream board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

10
boards/rak_wismesh_pocket.conf Normal file
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@@ -0,0 +1,10 @@
# RAK WisMesh Pocket — nRF52840 + SX1262
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

17
boards/rak_wismesh_pocket.overlay Normal file
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@@ -0,0 +1,17 @@
/*
* RAK WisMesh Pocket — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI1 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

10
boards/rak_wismesh_tag.conf Normal file
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@@ -0,0 +1,10 @@
# RAK WisMesh Tag — nRF52840 + SX1262
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# SX1262 driver
CONFIG_LORA_SX12XX=y

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boards/rak_wismesh_tag.overlay Normal file
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/*
* RAK WisMesh Tag — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: SX1262 on SPI1 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

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boards/seeed/seeed_wio_tracker/Kconfig.defconfig Normal file
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if BOARD_SEEED_WIO_TRACKER
config BOARD
default "seeed_wio_tracker"
endif # BOARD_SEEED_WIO_TRACKER

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boards/seeed/seeed_wio_tracker/Kconfig.seeed_wio_tracker Normal file
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config BOARD_SEEED_WIO_TRACKER
select SOC_NRF52840_QIAA

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boards/seeed/seeed_wio_tracker/board.cmake Normal file
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# Seeed Wio Tracker 1110 — board.cmake
# Uses nrfjprog or pyocd for flashing via SWD.
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(pyocd "--target=nrf52840")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

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boards/seeed/seeed_wio_tracker/board.yml Normal file
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board:
name: seeed_wio_tracker
full_name: "Seeed Wio Tracker 1110"
vendor: seeed
url: https://wiki.seeedstudio.com/wio_tracker_1110_intro/
socs:
- name: nrf52840

47
boards/seeed/seeed_wio_tracker/seeed_wio_tracker-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Seeed Wio Tracker 1110 — pin control definitions
* NOTE: GPIO numbers are placeholders. Verify from schematic.
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 25)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 24)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 25)>,
<NRF_PSEL(UART_RX, 0, 24)>;
low-power-enable;
};
};
/* SPI1 for LR1110 — verify pins from Wio Tracker 1110 schematic */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
<NRF_PSEL(SPIM_MOSI, 0, 22)>,
<NRF_PSEL(SPIM_MISO, 0, 23)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 21)>,
<NRF_PSEL(SPIM_MOSI, 0, 22)>,
<NRF_PSEL(SPIM_MISO, 0, 23)>;
low-power-enable;
};
};
};

117
boards/seeed/seeed_wio_tracker/seeed_wio_tracker.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* Seeed Wio Tracker 1110 — Device Tree Source
* SoC: nRF52840
* Radio: Semtech LR1110 (LoRa + GNSS multi-protocol transceiver)
*
* NOTE: GPIO pin numbers are placeholders. Verify against the
* Wio Tracker 1110 schematic before using with real hardware.
* The LR1110 SPI interface differs from SX126x: it uses 2-byte
* opcodes and requires the BUSY pin to be checked between transactions.
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "seeed_wio_tracker-pinctrl.dtsi"
/ {
model = "Seeed Wio Tracker 1110";
compatible = "seeed,wio-tracker-1110";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
led0 = &led_green;
};
leds {
compatible = "gpio-leds";
led_green: led_0 {
/* TODO: verify LED GPIO from Wio Tracker 1110 schematic */
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
/*
* LR1110 on SPI1
* Pin assignments are placeholders — must be verified from schematic.
* The LR1110 BUSY and EVENT (DIO9) pins are both required by the driver.
*/
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,lr11xx";
reg = <0>;
spi-max-frequency = <4000000>;
reset-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
event-gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

8
boards/seeed/seeed_wio_tracker/seeed_wio_tracker_defconfig Normal file
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CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_SEEED_WIO_TRACKER=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_NRFX_POWER=y

10
boards/seeed_wio_tracker.conf Normal file
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# Seeed Wio Tracker 1110 — nRF52840 + LR1110
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# LR11xx driver (out-of-tree)
CONFIG_LORA_LR11XX=y

17
boards/seeed_wio_tracker.overlay Normal file
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/*
* Seeed Wio Tracker 1110 — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: LR1110 on SPI1 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};

6
boards/sensecap/sensecap_t1000e/Kconfig.defconfig Normal file
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if BOARD_SENSECAP_T1000E
config BOARD
default "sensecap_t1000e"
endif # BOARD_SENSECAP_T1000E

2
boards/sensecap/sensecap_t1000e/Kconfig.sensecap_t1000e Normal file
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config BOARD_SENSECAP_T1000E
select SOC_NRF52840_QIAA

6
boards/sensecap/sensecap_t1000e/board.cmake Normal file
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# SenseCAP T1000-E — board.cmake
# Uses nrfjprog or pyocd for flashing via SWD.
board_runner_args(nrfjprog "--nrf-family=NRF52")
board_runner_args(pyocd "--target=nrf52840")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

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boards/sensecap/sensecap_t1000e/board.yml Normal file
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board:
name: sensecap_t1000e
full_name: "SenseCAP T1000-E"
vendor: sensecap
url: https://www.seeedstudio.com/SenseCAP-Card-Tracker-T1000-E-p-5913.html
socs:
- name: nrf52840

47
boards/sensecap/sensecap_t1000e/sensecap_t1000e-pinctrl.dtsi Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* SenseCAP T1000-E — pin control definitions
* NOTE: GPIO numbers are placeholders. Verify from schematic.
*/
#include <nordic/nrf52840.dtsi>
#include <dt-bindings/pinctrl/nrf-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 25)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 24)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 25)>,
<NRF_PSEL(UART_RX, 0, 24)>;
low-power-enable;
};
};
/* SPI1 for LR1110 — verify pins from T1000-E schematic */
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 17)>,
<NRF_PSEL(SPIM_MOSI, 0, 18)>,
<NRF_PSEL(SPIM_MISO, 0, 19)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 17)>,
<NRF_PSEL(SPIM_MOSI, 0, 18)>,
<NRF_PSEL(SPIM_MISO, 0, 19)>;
low-power-enable;
};
};
};

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boards/sensecap/sensecap_t1000e/sensecap_t1000e.dts Normal file
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/*
* SPDX-License-Identifier: Apache-2.0
*
* SenseCAP T1000-E — Device Tree Source
* SoC: nRF52840
* Radio: Semtech LR1110 (LoRa + GNSS multi-protocol transceiver)
*
* NOTE: GPIO pin numbers are placeholders. Verify against the
* SenseCAP T1000-E schematic before using with real hardware.
* The T1000-E is a different product from the Seeed Wio Tracker 1110,
* despite sharing the same SoC and radio chip.
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
#include "sensecap_t1000e-pinctrl.dtsi"
/ {
model = "SenseCAP T1000-E";
compatible = "sensecap,t1000e";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
aliases {
lora0 = &lora;
led0 = &led_green;
};
leds {
compatible = "gpio-leds";
led_green: led_0 {
/* TODO: verify LED GPIO from T1000-E schematic */
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
/*
* LR1110 on SPI1
* Pin assignments are placeholders — must be verified from schematic.
*/
&spi1 {
compatible = "nordic,nrf-spim";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,lr11xx";
reg = <0>;
spi-max-frequency = <4000000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
busy-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
event-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000C000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x00067000>;
};
slot1_partition: partition@73000 {
label = "image-1";
reg = <0x00073000 0x00067000>;
};
storage_partition: partition@da000 {
label = "storage";
reg = <0x000da000 0x00006000>;
};
};
};

8
boards/sensecap/sensecap_t1000e/sensecap_t1000e_defconfig Normal file
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CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_SENSECAP_T1000E=y
CONFIG_FLASH=y
CONFIG_FLASH_MAP=y
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_NRFX_POWER=y

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boards/sensecap_t1000e.conf Normal file
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# SenseCAP T1000-E — nRF52840 + LR1110
# Uses USB CDC-ACM
CONFIG_LORAMODEM_KISS_IFACE_USB=y
CONFIG_USB_DEVICE_STACK=y
CONFIG_USB_CDC_ACM=y
CONFIG_UART_LINE_CTRL=y
# LR11xx driver (out-of-tree)
CONFIG_LORA_LR11XX=y

17
boards/sensecap_t1000e.overlay Normal file
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/*
* SenseCAP T1000-E — application DTS overlay
* KISS interface: USB CDC-ACM
* LoRa: LR1110 on SPI1 (defined in custom board DTS)
*/
/ {
chosen {
loramodem,kiss-uart = &cdc_acm_uart0;
};
};
&zephyr_udc0 {
cdc_acm_uart0: cdc_acm_uart0 {
compatible = "zephyr,cdc-acm-uart";
};
};