# 0 "/Users/wijnand/zephyrproject/zephyr/misc/empty_file.c"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts" 1

/dts-v1/;

# 1 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi" 1

/dts-v1/;

# 1 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi" 1 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 1 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/dts/common/mem.h" 1 3 4
# 7 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/dts/common/freq.h" 1 3 4
# 8 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/xtensa.dtsi" 1 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/dts/common/skeleton.dtsi" 1 3 4
# 9 "/Users/wijnand/zephyrproject/zephyr/dts/common/skeleton.dtsi" 3 4
/ {
 #address-cells = <1>;
 #size-cells = <1>;

 chosen {};

 aliases {};
};
# 8 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/xtensa.dtsi" 2 3 4

/ {
 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  ranges;
 };
};
# 9 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 1 3 4
# 9 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 1 3 4
# 19 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 1 3 4
# 34 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 1 3 4
# 18 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 1 3 4
# 1465 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_listify.h" 1 3 4
# 1466 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_loops.h" 2 3 4
# 19 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 203 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal_is_eq.h" 1 3 4
# 204 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 234 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_inc.h" 1 3 4
# 235 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_dec.h" 1 3 4
# 238 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal_util_x2.h" 1 3 4
# 241 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_internal.h" 2 3 4
# 35 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/sys/util_macro.h" 2 3 4
# 20 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/dt-util.h" 2 3 4
# 10 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/adc/adc.h" 2 3 4
# 10 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/gpio/gpio.h" 1 3 4
# 11 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/i2c/i2c.h" 1 3 4
# 12 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/clock/esp32s3_clock.h" 1 3 4
# 13 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h" 1 3 4
# 14 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4
# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h" 1 3 4
# 15 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi" 2 3 4

/ {
 aliases {
  die-temp0 = &coretemp;
 };

 chosen {
  zephyr,canbus = &twai;
  zephyr,entropy = &trng0;
  zephyr,flash-controller = &flash;
  zephyr,bt-hci = &esp32_bt_hci;
 };

 cpus {
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "espressif,xtensa-lx7";
   reg = <0>;
   cpu-power-states = <&light_sleep &deep_sleep>;
   clock-source = <1U>;
   clock-frequency = <(((240) * 1000) * 1000)>;
   xtal-freq = <(((40) * 1000) * 1000)>;
  };

  cpu1: cpu@1 {
   reg = <1>;
  };

  power-states {
   light_sleep: light_sleep {
    compatible = "zephyr,power-state";
    power-state-name = "standby";
    min-residency-us = <1000>;
    exit-latency-us = <50>;
   };

   deep_sleep: deep_sleep {

    power-state-name = "soft-off";
    status = "disabled";
   };
  };
 };

 wifi: wifi {
  compatible = "espressif,esp32-wifi";
  status = "disabled";
 };

 esp32_bt_hci: esp32_bt_hci {
  compatible = "espressif,esp32-bt-hci";
  bt-hci-vs-ext;
 };

 pinctrl: pin-controller {
  compatible = "espressif,esp32-pinctrl";
  status = "okay";
 };

 clock: clock {
  compatible = "espressif,esp32-clock";
  fast-clk-src = <1>;
  slow-clk-src = <0>;
  #clock-cells = <1>;
 };

 soc {
  ranges;

  icache0: memory@42000000 {
   compatible = "zephyr,memory-region";
   reg = <0x42000000 (((32) * 1024) * 1024)>;
   zephyr,memory-region = "ICACHE0";
  };

  dcache0: memory@3c000000 {
   reg = <0x3c000000 (((32) * 1024) * 1024)>;
   zephyr,memory-region = "DCACHE0";

   psram0: psram0 {
    compatible = "espressif,esp32-psram";
    size = <0x0>;
   };
  };

  sram0: memory@40370000 {
   compatible = "zephyr,memory-region", "mmio-sram";
   reg = <0x40370000 ((32) * 1024)>;
   zephyr,memory-region = "SRAM0";
  };

  sram1: memory@3fc88000 {
   reg = <0x3fc88000 ((416) * 1024)>;
   zephyr,memory-region = "SRAM1";
  };

  sram2: memory@3fcf0000 {
   reg = <0x3fcf0000 ((64) * 1024)>;
   zephyr,memory-region = "SRAM2";
  };

  ipmmem0: memory@3fce5000 {
   compatible = "mmio-sram";
   reg = <0x3fce5000 0x400>;
  };

  shm0: memory@3fce5400 {
   reg = <0x3fce5400 0x4000>;
  };

  ipm0: ipm@3fce9400 {
   compatible = "espressif,esp32-ipm";
   reg = <0x3fce9400 0x8>;
   status = "disabled";
   shared-memory = <&ipmmem0>;
   shared-memory-size = <0x400>;
   interrupts = <79 0 0>,
         <80 0 0>;
   interrupt-parent = <&intc>;
  };

  mbox0: mbox@3fce9408 {
   compatible = "espressif,mbox-esp32";
   reg = <0x3fce9408 0x8>;
         <80 0 0>;
   #mbox-cells = <1>;
  };

  rtc_slow_ram: memory@50000000 {
   reg = <0x50000000 ((8) * 1024)>;
   zephyr,memory-region = "RTC_SLOW_RAM";
  };

  rtc_fast_ram: memory@600fe000 {
   reg = <0x600fe000 ((8) * 1024)>;
   zephyr,memory-region = "RTC_FAST_RAM";
  };

  intc: interrupt-controller@600c2000 {
   #interrupt-cells = <3>;
   #address-cells = <0>;
   compatible = "espressif,esp32-intc";
   interrupt-controller;
   reg = <0x600c2000 0x1000>;
   status = "okay";
  };

  xt_wdt: xt_wdt@60021004 {
   compatible = "espressif,esp32-xt-wdt";
   reg = <0x60021004 0x4>;
   clocks = <&clock 12>;
   interrupts = <39 0 0>;
  };

  rtc_timer: rtc_timer@60008004 {
   reg = <0x60008004 0xc>;
   compatible = "espressif,esp32-rtc-timer";
  };

  flash: flash-controller@60002000 {
   compatible = "espressif,esp32-flash-controller";
   reg = <0x60002000 0x1000>;
   #address-cells = <1>;
   #size-cells = <1>;

   flash0: flash@0 {
    compatible = "soc-nv-flash";
    erase-block-size = <4096>;
    write-block-size = <4>;

   };
  };

  uart0: uart@60000000 {
   compatible = "espressif,esp32-uart";
   reg = <0x60000000 0x1000>;
   interrupts = <27 0 0>;
   clocks = <&clock 101>;
  };

  uart1: uart@60010000 {
   reg = <0x60010000 0x1000>;
   interrupts = <28 0 0>;
   clocks = <&clock 0>;
  };

  uart2: uart@6002e000 {
   reg = <0x6002e000 0x1000>;
   interrupts = <29 0 0>;
   clocks = <&clock 1>;
  };

  gpio: gpio {
   compatible = "simple-bus";
   gpio-map-mask = <0xffffffe0 0xffffffc0>;
   gpio-map-pass-thru = <0x1f 0x3f>;
   gpio-map = <0x00 0x0 &gpio0 0x0 0x0
        0x20 0x0 &gpio1 0x0 0x0>;
   #gpio-cells = <2>;
   ranges;

   gpio0: gpio@60004000 {
    compatible = "espressif,esp32-gpio";
    gpio-controller;
    #gpio-cells = <2>;
    reg = <0x60004000 0x800>;
    interrupts = <16 0 0>;
    interrupt-parent = <&intc>;

    ngpios = <32>;
   };

   gpio1: gpio@60004800 {
    reg = <0x60004800 0x800>;
    ngpios = <22>;
   };
  };

  touch: touch@6000885c {
   compatible = "espressif,esp32-touch";
   reg = <0x6000885c 0x88 0x60008908 0x18>;
  };

  i2c0: i2c@60013000 {
   compatible = "espressif,esp32-i2c";
   #size-cells = <0>;
   reg = <0x60013000 ((4) * 1024)>;
   interrupts = <42 0 0>;
   clocks = <&clock 103>;
  };

  i2c1: i2c@60027000 {
   reg = <0x60027000 ((4) * 1024)>;
   interrupts = <43 0 0>;
   clocks = <&clock 104>;
  };

  i2s0: i2s@6000f000 {
   compatible = "espressif,esp32-i2s";
   reg = <0x6000f000 0x1000>;
   interrupts = <25 0 0>;
   clocks = <&clock 105>;
   dmas = <&dma 2>, <&dma 3>;
   dma-names = "rx", "tx";
   unit = <0>;
  };

  i2s1: i2s@6002d000 {
   reg = <0x6002d000 0x1000>;
   interrupts = <26 0 0>;
   clocks = <&clock 106>;
   dmas = <&dma 4>, <&dma 5>;
   unit = <1>;
  };

  spi2: spi@60024000 {
   compatible = "espressif,esp32-spi";
   reg = <0x60024000 ((4) * 1024)>;
   interrupts = <21 0 0>;
   clocks = <&clock 115>;
   dma-host = <0>;
  };

  spi3: spi@60025000 {
   reg = <0x60025000 ((4) * 1024)>;
   interrupts = <22 0 0>;
   clocks = <&clock 116>;
   dma-host = <1>;
  };

  coretemp: coretemp@60008800 {
   compatible = "espressif,esp32-temp";
   friendly-name = "coretemp";
   reg = <0x60008800 0x4>;
  };

  adc0: adc@60040000 {
   compatible = "espressif,esp32-adc";
   reg = <0x60040000 4>;
   clocks = <&clock 128>;
   unit = <1>;
   channel-count = <10>;
   #io-channel-cells = <1>;
  };

  adc1: adc@60040004 {
   reg = <0x60040004 4>;
   unit = <2>;
  };

  twai: can@6002b000 {
   compatible = "espressif,esp32-twai";
   reg = <0x6002b000 ((4) * 1024)>;
   interrupts = <37 0 0>;
   clocks = <&clock 118>;
  };

  lcd_cam: lcd_cam@60041000 {
   compatible = "espressif,esp32-lcd-cam";
   reg = <0x60041000 ((4) * 1024)>;
   clocks = <&clock 2>;
   interrupts = <24 0 0>;
   dmas = <&dma 6>, <&dma 7>;

   lcd_cam_dvp: lcd_cam_dvp {
    compatible = "espressif,esp32-lcd-cam-dvp";
   };

   lcd_cam_disp: lcd_cam_disp {
    compatible = "espressif,esp32-lcd-cam-mipi-dbi";
    #address-cells = <1>;
    #size-cells = <0>;
   };
  };

  usb_serial: uart@60038000 {
   compatible = "espressif,esp32-usb-serial";
   reg = <0x60038000 ((4) * 1024)>;
   interrupts = <96 0 0>;
   clocks = <&clock 102>;
  };

  usb_otg: usb_otg@60080000 {
   compatible = "espressif,esp32-usb-otg", "snps,dwc2";
   reg = <0x60080000 ((256) * 1024)>;
   interrupts = <38 0 0>;
   num-out-eps = <6>;
   num-in-eps = <6>;
   ghwcfg1 = <0x00000000>;
   ghwcfg2 = <0x224dd930>;
   ghwcfg4 = <0xd3f0a030>;
  };

  timer0: counter@6001f000 {
   compatible = "espressif,esp32-timer";
   reg = <0x6001f000 ((4) * 1024)>;
   clocks = <&clock 3>;
   group = <0>;
   index = <0>;
   interrupts = <50 0 0>;

   counter {
    compatible = "espressif,esp32-counter";
   };
  };

  timer1: counter@6001f024 {
   reg = <0x6001f024 ((4) * 1024)>;
   index = <1>;
   interrupts = <51 0 0>;

   counter {
   };
  };

  timer2: counter@60020000 {
   reg = <0x60020000 ((4) * 1024)>;
   clocks = <&clock 4>;
   group = <1>;
   interrupts = <53 0 0>;

   counter {
   };
  };

  timer3: counter@60020024 {
   reg = <0x60020024 ((4) * 1024)>;
   interrupts = <54 0 0>;

   counter {
   };
  };

  wdt0: watchdog@6001f048 {
   compatible = "espressif,esp32-watchdog";
   reg = <0x6001f048 0x20>;
   interrupts = <52 0 0>;
  };

  wdt1: watchdog@60020048 {
   reg = <0x60020048 0x20>;
   interrupts = <55 0 0>;
  };

  trng0: trng@6003507c {
   compatible = "espressif,esp32-trng";
   reg = <0x6003507c 0x4>;
   clocks = <&clock 6>;
  };

  ledc0: ledc@60019000 {
   compatible = "espressif,esp32-ledc";
   #pwm-cells = <3>;
   reg = <0x60019000 ((4) * 1024)>;
   clocks = <&clock 100>;
  };

  mcpwm0: mcpwm@6001e000 {
   compatible = "espressif,esp32-mcpwm";
   reg = <0x6001e000 ((4) * 1024)>;
   interrupts = <31 0 0>;
   clocks = <&clock 107>;
  };

  mcpwm1: mcpwm@6002c000 {
   reg = <0x6002c000 ((4) * 1024)>;
   interrupts = <32 0 0>;
   clocks = <&clock 108>;
  };

  pcnt: pcnt@60017000 {
   compatible = "espressif,esp32-pcnt";
   reg = <0x60017000 ((4) * 1024)>;
   interrupts = <41 0 0>;
   clocks = <&clock 113>;
  };

  dma: dma@6003f000 {
   compatible = "espressif,esp32-gdma";
   reg = <0x6003f000 ((4) * 1024)>;
   #dma-cells = <1>;
   interrupts = <66 0
          (1<<8)>,
         <71 0
          (1<<8)>,
         <67 0
          (1<<8)>,
         <72 0
          (1<<8)>,
         <68 0
          (1<<8)>,
         <73 0
          (1<<8)>,
         <69 0
          (1<<8)>,
         <74 0
          (1<<8)>,
         <70 0
          (1<<8)>,
         <75 0
          (1<<8)>;
   clocks = <&clock 126>;
   dma-channels = <10>;
   dma-buf-addr-alignment = <4>;
  };

  sdhc: sdhc@60028000 {
   compatible = "espressif,esp32-sdhc";
   reg = <0x60028000 0x1000>;
   interrupts = <30 0 0>;
   clocks = <&clock 117>;

   sdhc0: sdhc@0 {
    compatible = "espressif,esp32-sdhc-slot";
    reg = <0>;
   };

   sdhc1: sdhc@1 {
    reg = <1>;
   };
  };

  sha: sha@6003b000 {
   compatible = "espressif,esp32-sha";
   reg = <0x6003b000 0x100>;
   clocks = <&clock 122>;
  };

  aes: aes@6003a000 {
   compatible = "espressif,esp32-aes";
   reg = <0x6003a000 0x1000>;
   clocks = <&clock 121>;
  };
 };
};
# 8 "/Users/wijnand/zephyrproject/zephyr/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi" 2 3 4

&flash0 {
 reg = <0x0 (((8) * 1024) * 1024)>;
};

&psram0 {
 size = <(((8) * 1024) * 1024)>;
};
# 10 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi" 2
# 1 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi" 1

# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h" 1 3 4
# 8 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi" 2

# 1 "/Users/wijnand/zephyrproject/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h" 1 3 4
# 10 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi" 2

&pinctrl {
 uart0_default: uart0_default {
  group1 {
   pinmux = <(((43 & 0x3FU) << 0U) | ((0x1FFU & 0x1FFU) << 6U) | ((12 & 0x1FFU) << 15U))>;
   output-high;
  };

  group2 {
   pinmux = <(((44 & 0x3FU) << 0U) | ((12 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>;
   bias-pull-up;
  };
 };

 spim2_default: spim2_default {
  group1 {
   pinmux = <(((8 & 0x3FU) << 0U) | ((102 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((7 & 0x3FU) << 0U) | ((0x1FFU & 0x1FFU) << 6U) | ((101 & 0x1FFU) << 15U))>;
  };

  group2 {
   pinmux = <(((9 & 0x3FU) << 0U) | ((0x1FFU & 0x1FFU) << 6U) | ((103 & 0x1FFU) << 15U))>;
   output-low;
  };
 };

 i2c0_default: i2c0_default {
  group1 {
   pinmux = <(((5 & 0x3FU) << 0U) | ((90 & 0x1FFU) << 6U) | ((90 & 0x1FFU) << 15U))>,
     <(((6 & 0x3FU) << 0U) | ((89 & 0x1FFU) << 6U) | ((89 & 0x1FFU) << 15U))>;
   drive-open-drain;
  };
 };

 i2c1_default: i2c1_default {
  group1 {
   pinmux = <(((40 & 0x3FU) << 0U) | ((92 & 0x1FFU) << 6U) | ((92 & 0x1FFU) << 15U))>,
     <(((39 & 0x3FU) << 0U) | ((91 & 0x1FFU) << 6U) | ((91 & 0x1FFU) << 15U))>;
  };
 };

 lcd_cam_default: lcd_cam_default {
  group1 {
   pinmux = <(((10 & 0x3FU) << 0U) | ((0x1FFU & 0x1FFU) << 6U) | ((149 & 0x1FFU) << 15U))>;
   output-enable;
  };

  group2 {
   pinmux = <(((38 & 0x3FU) << 0U) | ((152 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((47 & 0x3FU) << 0U) | ((150 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((13 & 0x3FU) << 0U) | ((149 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((15 & 0x3FU) << 0U) | ((133 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((17 & 0x3FU) << 0U) | ((134 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((18 & 0x3FU) << 0U) | ((135 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((16 & 0x3FU) << 0U) | ((136 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((14 & 0x3FU) << 0U) | ((137 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((12 & 0x3FU) << 0U) | ((138 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((11 & 0x3FU) << 0U) | ((139 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>,
     <(((48 & 0x3FU) << 0U) | ((140 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>;
   input-enable;
   bias-disable;
  };
 };

 twai_default: twai_default {
  group1 {
   pinmux = <(((3 & 0x3FU) << 0U) | ((0x1FFU & 0x1FFU) << 6U) | ((116 & 0x1FFU) << 15U))>,
     <(((4 & 0x3FU) << 0U) | ((116 & 0x1FFU) << 6U) | ((0x1FFU & 0x1FFU) << 15U))>;
  };
 };
};
# 11 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi" 2
# 1 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/seeed_xiao_connector.dtsi" 1

/ {
 xiao_d: connector {
  compatible = "seeed,xiao-gpio";
  #gpio-cells = <2>;
  gpio-map-mask = <0xffffffff 0xffffffc0>;
  gpio-map-pass-thru = <0 0x3f>;
  gpio-map = <0 0 &gpio0 1 0>,
      <1 0 &gpio0 2 0>,
      <2 0 &gpio0 3 0>,
      <3 0 &gpio0 4 0>,
      <4 0 &gpio0 5 0>,
      <5 0 &gpio0 6 0>,
      <6 0 &gpio1 11 0>,
      <7 0 &gpio1 12 0>,
      <8 0 &gpio0 7 0>,
      <9 0 &gpio0 8 0>,
      <10 0 &gpio0 9 0>;
 };
};

xiao_spi: &spi2 {};

xiao_i2c: &i2c0 {};

xiao_serial: &uart0 {};

xiao_adc: &adc0 {};
# 12 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi" 2

/ {
 chosen {
  zephyr,sram = &sram1;
  zephyr,console = &usb_serial;
  zephyr,shell-uart = &usb_serial;
  zephyr,flash = &flash0;
  zephyr,code-partition = &slot0_partition;
 };

 aliases {
  i2c-0 = &i2c0;
  watchdog0 = &wdt0;
  led0 = &led0;
 };

 leds {
  compatible = "gpio-leds";

  led0: led_0 {
   gpios = <&gpio0 21 (1 << 0)>;
   label = "BUILTIN LED";
  };
 };
};

&usb_serial {
 status = "okay";
};

&uart0 {
 current-speed = <115200>;
 pinctrl-0 = <&uart0_default>;
 pinctrl-names = "default";
};

&i2c0 {
 clock-frequency = <100000>;
 pinctrl-0 = <&i2c0_default>;
};

&trng0 {
};

&spi2 {
 #size-cells = <0>;
 pinctrl-0 = <&spim2_default>;
};

&gpio0 {
};

&gpio1 {
};

&wdt0 {
};

&twai {
 pinctrl-0 = <&twai_default>;
};

&timer0 {
};

&timer1 {
};

&esp32_bt_hci {
};

&wifi {
};
# 10 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts" 2
# 11 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi"
&pinctrl {
  group1 {
  };

  group2 {
  };
 };

  group1 {
  };

  group2 {
  };
 };

  group1 {
  };
 };

  group1 {
  };
 };

  group1 {
  };

  group2 {
  };
 };

  group1 {
  };
 };
};
# 11 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts" 2

/ {
 };
};

# 12 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts" 2
# 1 "/Users/wijnand/zephyrproject/zephyr/dts/vendor/espressif/partitions_0x0_amp.dtsi" 1 3 4

# 1 "/Users/wijnand/zephyrproject/zephyr/dts/vendor/espressif/partitions_0x0_amp_4M.dtsi" 1 3 4

&flash0 {
 partitions {
  compatible = "fixed-partitions";

  boot_partition: partition@0 {
   label = "mcuboot";
   reg = <0x0 ((64) * 1024)>;
  };

  sys_partition: partition@10000 {
   label = "sys";
   reg = <0x10000 ((64) * 1024)>;
  };

  slot0_partition: partition@20000 {
   label = "image-0";
   reg = <0x20000 ((1344) * 1024)>;
  };

  slot1_partition: partition@170000 {
   label = "image-1";
   reg = <0x170000 ((1344) * 1024)>;
  };

  slot0_appcpu_partition: partition@2c0000 {
   label = "image-0-appcpu";
   reg = <0x2c0000 ((448) * 1024)>;
  };

  slot1_appcpu_partition: partition@330000 {
   label = "image-1-appcpu";
   reg = <0x330000 ((448) * 1024)>;
  };

  slot0_lpcore_partition: partition@3a0000 {
   label = "image-0-lpcore";
   reg = <0x3a0000 ((32) * 1024)>;
  };

  slot1_lpcore_partition: partition@3a8000 {
   label = "image-1-lpcore";
   reg = <0x3a8000 ((32) * 1024)>;
  };

  storage_partition: partition@3b0000 {
   label = "storage";
   reg = <0x3b0000 ((192) * 1024)>;
  };

  scratch_partition: partition@3e0000 {
   label = "image-scratch";
   reg = <0x3e0000 ((124) * 1024)>;
  };

  coredump_partition: partition@3ff000 {
   label = "coredump";
   reg = <0x3ff000 ((4) * 1024)>;
  };
 };
};
# 8 "/Users/wijnand/zephyrproject/zephyr/dts/vendor/espressif/partitions_0x0_amp.dtsi" 2 3 4
# 13 "/Users/wijnand/zephyrproject/zephyr/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts" 2

/ {
 model = "Seeed Xiao ESP32S3 PROCPU";
 compatible = "seeed,xiao-esp32s3";
};
# 0 "<command-line>" 2
# 1 "/Volumes/External/Work/radio/loramodem/boards/seeed/xiao_wio_sx1262/xiao_wio_sx1262.overlay" 1
# 17 "/Volumes/External/Work/radio/loramodem/boards/seeed/xiao_wio_sx1262/xiao_wio_sx1262.overlay"
/ {
 chosen {
  loramodem,kiss-uart = &usb_serial;
 };
 aliases {
  lora0 = &lora;
 };
};

&spi2 {
 cs-gpios = <&gpio0 3 (1 << 0)>;

 lora: lora@0 {
  compatible = "semtech,sx1262";
  reg = <0>;
  spi-max-frequency = <4000000>;
  reset-gpios = <&gpio0 2 (1 << 0)>;
  busy-gpios = <&gpio0 1 (0 << 0)>;
  dio1-gpios = <&gpio0 0 (0 << 0)>;
  dio2-tx-enable;

  tx-enable-gpios = <&gpio0 4 (0 << 0)>;

 };
};

&gpio0 {
};

&gpio1 {
};
# 1 "/Users/wijnand/zephyrproject/zephyr/misc/empty_file.c"

Signify that this node should result in a dedicated linker script
memory region in the final executable. The region address and size
is taken from the <reg> property, while the name is the value of
this property.

Indicates the operational status of the hardware or other
resource that the node represents. In particular:

  - "okay" means the resource is operational and, for example,
    can be used by device drivers
  - "disabled" means the resource is not operational and the system
    should treat it as if it is not present

For details, see "2.3.4 status" in Devicetree Specification v0.4.

This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.

The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.

The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.

For details, see "2.3.1 compatible" in Devicetree Specification v0.4.

Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).

The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.

For details, see "2.3.6 reg" in Devicetree Specification v0.4.

Optional names given to each register block in the "reg" property.
For example:

  / {
       soc {
           #address-cells = <1>;
           #size-cells = <1>;

           uart@1000 {
               reg = <0x1000 0x2000>, <0x3000 0x4000>;
               reg-names = "foo", "bar";
           };
       };
  };

The uart@1000 node has two register blocks:

  - one with base address 0x1000, size 0x2000, and name "foo"
  - another with base address 0x3000, size 0x4000, and name "bar"

Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.

Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.

If present, this refers to the node which handles interrupts generated
by this device.

Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.

For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.

Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:

  https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

Optional names given to each clock provider in the "clocks" property.

This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree

This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.

Optional names given to the DMA channel specifiers in the "dmas" property.

Optional names given to the IO channel specifiers in the "io-channels" property.

Optional names given to the mbox specifiers in the "mboxes" property.

Optional names given to the power domain specifiers in the "power-domains" property.

Optional names given to the hwlock specifiers in the "hwlocks" property.

Do not initialize device automatically on boot. Device should be manually
initialized using device_init().

Property to identify that a device can be used as wake up source.

When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.

Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.

Automatically configure the device for runtime power management after the
init function runs.

Set attributes such as read-only or executable for the linker script
memory region. The string set here will be specified in parentheses
after the area name in the linker script.

Signify that this node should result in a dedicated MPU region.
Deprecated in favor of 'zephyr,memory-attr'.

Attribute or set of attributes (bitmask) for the memory region. See
'include/zephyr/dt-bindings/memory-attr/memory-attr.h' for a
comprehensive list with description of possible values.

ESP32 XT Watchdog Timer.

This watchdog timer can detect oscillation failure of the RTC_SLOW_CLK_SRC_XTAL32K.
When such a failure is detected the hardware automatically switch to
ESP32_RTC_SLOW_CLK_SRC_RC_SLOW.

This feature is only available for ESP32S2,ESP32C3 and ESP32S3.

RTC fast clock source.
- 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
ESP32_RTC_FAST_CLK_SRC_XTAL_D4 Main XTAL divided by 4 (ESP32/S2)
- 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz

RTC slow clock source. Default to
- 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32)
- 1: ESP32_RTC_SLOW_CLK_SRC_XTAL32K - 32,768U KHz
- 2: ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 - 17,5 MHz
- 9: ESP32_RTC_SLOW_CLK_32K_EXT_OSC - External 32k oscillator connected to 32K_XP pin

ESP32 Counter Driver based on RTC Main Timer.

Any reset/sleep mode, except for the power-up reset, will not
stop or reset the RTC Timer. This behavior may be handy when
supporting applications that need to keep a timing baseline on
such situations.

There is also no need to enable the RTC Timer node, it starts
running from power-up.

Fixed partitions of a flash (or other non-volatile storage) memory.

Note that the usual name for this node is 'partitions'.
The fixed-partitions node should be a child of the flash
memory node. Note also that the flash memory node is usually
different from the node representing the flash controller
IP block.

Above, slot0_partition's register address 0xc000 means that
the partition begins at that offset from the parent flash
memory flash0's base address. That is, partition addresses
are relative; physical addresses must be calculated by adding
the start address of flash0 in memory to each partition's
reg address.

Number of cells required to represent a child node's
reg property address. This must be large enough to
represent the start offset of each partition.

represent the size of each partition in bytes.

Each child node of the fixed-partitions node represents
an individual flash partition. These should usually
look like this:

  partition_nodelabel: partition@START_OFFSET {
          label = "human-readable-name";
          reg = <0xSTART_OFFSET 0xSIZE>;
  };

This should be in the format <OFFSET SIZE>, where OFFSET
is the offset of the flash partition relative to the base
address of the parent memory, and SIZE is the size of
the partition in bytes.

&flash0 {
        partitions {
                compatible = "fixed-partitions";
                #address-cells = <1>;
                #size-cells = <1>;

                boot_partition: partition@0 {
                        label = "mcuboot";
                        reg = <0x00000000 0x0000C000>;
                };
                slot0_partition: partition@c000 {
                        label = "image-0";
                        reg = <0x0000C000 0x00076000>;
                };
                slot1_partition: partition@82000 {
                        label = "image-1";
                        reg = <0x00082000 0x00076000>;
                };

                /*
                 * The flash starting at 0x000f8000 and ending at
                 * 0x000fffff is reserved for use by the application.
                 */

                /*
                 * Storage partition will be used by FCB/LittleFS/NVS
                 * if enabled.
                 */
                storage_partition: partition@f8000 {
                        label = "storage";
                        reg = <0x000f8000 0x00008000>;
                };
        };
};

Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

Names for the provided states. The number of names needs to match the
number of states.

Sets the number of stop bits. Defaults to standard of 1 if not specified.

Sets the number of data bits. Defaults to standard of 8 if not specified.

Enable the hardware RS485 half duplex mode.
Overrides hw-flow-control if both are set.
Using this mode, the pin assigned to DTR
is asserted during transmission.

Enable SLIP encoding on TX when using UART with DMA (async API).
When enabled, the UHCI hardware automatically encodes transmitted data
using SLIP framing (0xC0 -> 0xDB 0xDC, 0xDB -> 0xDB 0xDD).
Disabled by default to prevent unintended data corruption.

Enable SLIP decoding on RX when using UART with DMA (async API).
When enabled, the UHCI hardware automatically decodes received data
using SLIP framing (0xDB 0xDC -> 0xC0, 0xDB 0xDD -> 0xDB).

Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
and 2 for even parity, 3 for mark parity and 4 for space parity.
Default to none if not specified.

Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and
we use 1=Low, 0=High instead of 1=High, 0=Low.

Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and

Each array element represents pin muxing information of an individual
pin. The array elements are pre-declared macros taken from Espressif's
HAL.

Enable ESP GPIO pad hold during system sleep. When enabled, the pin
state is latched before entering sleep and remains unchanged while
the system is in low power mode.

enable input on pin (e.g. enable an input buffer, no effect on output)

enable output on a pin without actively driving it (e.g. enable an output
buffer)

This property indicates the number of in-use slots of available slots
for GPIOs. The typical example is something like this: the hardware
register is 32 bits wide, but only 18 of the bits have a physical
counterpart. The driver is generally written so that all 32 bits can
be used, but the IP block is reused in a lot of designs, some using
all 32 bits, some using 18 and some using 12. In this case, setting
"ngpios = <18>;" informs the driver that only the first 18 GPIOs, at
local offset 0 .. 17, are in use.  For cases in which there might be
holes in the slot range, this value should be the max slot number+1.

If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
this property contains an additional set of tuples which specify which GPIOs
are unusable. This property indicates the start and size of the GPIOs
that can't be used.

For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.

This is an array of strings defining the names of the GPIO lines
going out of the GPIO controller

Optional GPIO hog configuration.

Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a mechanism for
providing automatic GPIO configuration during driver initialization when Kconfig
CONFIG_GPIO_HOGS is enabled.

Each GPIO hog is represented as a child node of the GPIO controller.

Example:
  &gpio1 {
    mux-hog {
      gpio-hog;
      gpios = <10 GPIO_ACTIVE_HIGH>, <11 GPIO_ACTIVE_HIGH>;
      output-high;
    };
  };

  &gpio2 {
    test-hog {
      gpio-hog;
      gpios = <26 GPIO_ACTIVE_HIGH>;
      output-low;
      line-name = "test";
  };
};

This is an array of GPIO specifiers (e.g. pin, flags) to be hogged. The number of array
entries must be an integer multiple of the number of GPIO specifier cells for the parent
GPIO controller.

If this property is set, the GPIO is configured as an input. This property takes
precedence over the output-low and output-high properties.

If this property is set, the GPIO is configured as an output set to logical low. This
property takes precedence over the output-high property.

If this property is set, the GPIO is configured as an output set to logical high.

ESP32 touch sensor input

This defines a group of touch sensors that can generate input events. Each touch
sensor is defined in a child node of the touch-sensor node and defines a specific key
code.

Touch sensor IIR filter coefficient.
If not specified defaults to ESP32_TOUCH_FILTER_MODE_IIR_16.

Touch sensor noise threshold coefficient.
If not specified defaults to ESP32_TOUCH_FILTER_NOISE_THR_4_8TH.

Touch sensor jitter filter step size.
If not specified defaults to 4.

Touch sensor level of filter applied on the original data against large noise interference.
If not specified defaults to ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2.

Touch sensor channel sensibility in 100th.
If not specified defaults to 20.

#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>

&touch {
       compatible = "espressif,esp32-touch";
       status = "okay";

       debounce-interval-ms = <30>;
       href-microvolt = <27000000>;
       lref-microvolt = <500000>;
       href-atten-microvolt = <1000000>;
       filter-mode = <ESP32_TOUCH_FILTER_MODE_IIR_16>;
       filter-debounce-cnt = <1>;
       filter-noise-thr = <ESP32_TOUCH_FILTER_NOISE_THR_4_8TH>;
       filter-jitter-step = <4>;
       filter-smooth-level = <ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2>;

       touch_sensor_0 {
               channel-num = <1>;
               channel-sens = <20>;
               zephyr,code = <INPUT_KEY_0>;
       };
};

GPIO to which the I2C SCL signal is routed. This is only required
if the target SoC does not have support in hardware for clearing
the I2C bus in case of a communication failure

GPIO to which the I2C SDA signal is routed. This is only required

Timeout for unchanged SCL during clock stretching of the I2C target in
microseconds.

If not set or 0, the timeout is disabled or set to the maximum possible
value if the MCU does not support disabling the timeout.

ESP32 GDMA (General Direct Memory Access)

General Direct Memory Access (GDMA) is a feature that allows
peripheral-to-memory, memory-to-peripheral, and memory-to-memory
data transfer at a high speed.

The GDMA controller in ESP32-C3 has six independent channels,
three transmit channels and three receive channels.

Every channel can be connected to different peripherals.

ESP32C3's Peripherals with GDMA:
* SPI2
* UHCI0 (UART0/UART1)
* I2S
* AES (Not Supported yet)
* SHA (Not Supported yet)
* ADC

The GDMA controller in ESP32-S3 has ten independent channels,
five transmit channels and five receive channels. Only six are
supported, meaning three transmit and three receive channels.

ESP32S3's Peripherals with GDMA:
* SPI2
* SPI3
* UHCI0
* I2S0
* I2S1
* LCD/CAM
* ADC
* RMT (Not Supported yet)

Bitmask of available DMA channels in ascending order that are
not reserved by firmware and are available to the
kernel. i.e. first channel corresponds to LSB.

Memory address alignment requirement for DMA buffers used by the controller.

Memory size alignment requirement for DMA buffers used by the controller.

ESP32 SPI controller

Hardware chip select is directly handled via pinctrl. The reg property of
a child SPI device node corresponds to the hardware CS pin number configured
in pinctrl. ESP32 supports CS0-CS2, while ESP32-S2/S3/C2/C3/C6/H2 support
CS0-CS5.

Alternatively, GPIO-based chip selects can be used via the cs-gpios property.
When cs-gpios is defined, the hardware CS lines are disabled and the driver
uses GPIO pins for chip select control. In this case, the reg property of
child nodes corresponds to the index in the cs-gpios array.

Example with hardware CS (directly via pinctrl):

  &spi2 {
      pinctrl-0 = <&spim2_default>;  /* Must include CS signal */
      pinctrl-names = "default";

      device@0 {
          reg = <0>;  /* Uses hardware CS0 */
      };
  };

Example with GPIO CS:

  &spi2 {
      pinctrl-0 = <&spim2_default>;  /* CS signal optional */
      cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>,
                 <&gpio0 6 GPIO_ACTIVE_LOW>;

      device@0 {
          reg = <0>;  /* Uses first GPIO (gpio0 pin 5) */
      };
      device@1 {
          reg = <1>;  /* Uses second GPIO (gpio0 pin 6) */
      };
  };

Enable half-duplex communication mode.

Transmit data before receiving it, instead of simultaneously

Enable 3-wire mode

Use MOSI for both sending and receiving data

Support to toggle the CS while the clock toggles

Output clock on CS line if CS is active

Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX
routing mechanism instead, this avoids extra routing latency and makes
possible the use of operating frequencies higher than 20 MHz.

Refer to SoC's Technical Reference Manual to check which pins are
allowed to use this routing path.

Chip select setup time setting, see TRF for SOC for details of
timing applied.

Chip select hold time setting, see TRF for SOC for details of

Default MISO and MOSI pins GPIO level when idle. Defaults to high by default.

An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.

GPIO connected to the modem's NRESET signal.

This signal is open-drain, active-low as interpreted by the
modem.

GPIO connected to DIO1. This GPIO will be used as a generic
IRQ line from the chip.

Antenna switch TX enable GPIO. If set, the driver tracks the
state of the radio and controls the RF switch.

Antenna switch RX enable GPIO. If set, the driver tracks the

Use DIO2 to drive an RF switch selecting between the TX and RX
paths. When enabled, DIO2 goes high when the chip is
transmitting.

TCXO supply voltage controlled by DIO3 if present.

See constants in dt-bindings/lora/sx126x.h.

Enable RX boosted mode, which increases the power consumption of
RX mode by ~2mA in exchange for ~3dB sensitivity improvement.

Use the internal LDO instead of the internal DCDC. Increases power consumption.

Force usage of Low Data Rate Optimization even in cases where the symbol time is shorter than
16.38ms. Useful for designs using no TCXO or with bad heat dissipation.

Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
  0    SPI_FULL_DUPLEX
  2048 SPI_HALF_DUPLEX

Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
  0     SPI_FRAME_FORMAT_MOTOROLA
  32768 SPI_FRAME_FORMAT_TI

SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.

SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.

In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.

Delay in nanoseconds between SPI words.
Default of 0 is special value which will assume to mean half of the SCK period.

Delay in nanoseconds to be introduced by the controller after CS is asserted.
Also known as enable lead time.

Delay in nanoseconds to be introduced by the controller before the CS is de-asserted.
 Also known as enable lag time.

GPIO specifier that controls power to the device.

This property should be provided when the device has a dedicated
switch that controls power to the device.  The supply state is
entirely the responsibility of the device driver.

Contrast with vin-supply.

Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.

This property should be provided when device power is supplied
by a shared regulator.  The supply state is dependent on the
request status of all devices fed by the regulator.

Contrast with supply-gpios.  If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.

ESP32 internal temperature sensor

This peripheral supports a number of measurement ranges with different
precisions, based on the temperature range expected for the device to operate:

    Range (°C)      Error
    50 to 125       < 3°C
    20 to 100       < 2°C
    -10 to 80       < 1°C
    -30 to 50       < 2°C
    -40 to 20       < 3°C

The range and corresponding expected precision are selected through the
user-defined `range-min` and `range-max` properties. The default values
represent a typical operating temperature range while selecting the best
precision.

Human readable string describing the sensor. It can be used to
distinguish multiple instances of the same model (e.g., lid accelerometer
vs. base accelerometer in a laptop) to a host operating system.

This property is defined in the Generic Sensor Property Usages of the HID
Usage Tables specification
(https://usb.org/sites/default/files/hut1_3_0.pdf, section 22.5).

ESP32 ADC.

Possible available resolutions depends on the used chip.
  - ESP32     < 9,10,11,12 >
  - ESP32-S2  < 12 >
  - ESP32-C3  < 12 >
  - ESP32-S3  < 12 >
For chips with configurable resolution feature (ESP32),
maximum resolution will be used if not set explicitly.

Zephyr API is using gain unit to characterize ADC input.
To achieve compatibility we choose to select those gain,
which corresponds to the ESP32 ADC attenuation feature.

  ESP32,attenuation ~ zephyr,gain
  -----------------   -----------
  0 dB                ADC_GAIN_1
  2.5 dB              ADC_GAIN_4_5
  6 dB                ADC_GAIN_1_2
  11 dB               ADC_GAIN_1_4

In case unsupported gain is selected the adc_channel_setup()
would return ENOTSUP error.

Channel configuration.

All nodes using this binding must be named "channel", otherwise their
data will not be accessible for the ADC API macros.

This is based on Linux, documentation:
  https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/adc/adc.yaml

Gain selection:
- ADC_GAIN_1_6: x 1/6
- ADC_GAIN_1_5: x 1/5
- ADC_GAIN_1_4: x 1/4
- ADC_GAIN_2_7: x 2/7
- ADC_GAIN_1_3: x 1/3
- ADC_GAIN_2_5: x 2/5
- ADC_GAIN_1_2: x 1/2
- ADC_GAIN_2_3: x 2/3
- ADC_GAIN_4_5: x 4/5
- ADC_GAIN_1:   x 1
- ADC_GAIN_2:   x 2
- ADC_GAIN_3:   x 3
- ADC_GAIN_4:   x 4
- ADC_GAIN_6:   x 6
- ADC_GAIN_8:   x 8
- ADC_GAIN_12:  x 12
- ADC_GAIN_16:  x 16
- ADC_GAIN_24:  x 24
- ADC_GAIN_32:  x 32
- ADC_GAIN_64:  x 64
- ADC_GAIN_128: x 128

Reference selection:
- ADC_REF_VDD_1:     VDD
- ADC_REF_VDD_1_2:   VDD/2
- ADC_REF_VDD_1_3:   VDD/3
- ADC_REF_VDD_1_4:   VDD/4
- ADC_REF_INTERNAL:  Internal
- ADC_REF_EXTERNAL0: External, input 0
- ADC_REF_EXTERNAL1: External, input 1

This property can be used to specify the voltage (in millivolts)
of the reference selected for this channel, so that applications
can get that value if needed for some calculations.
For the internal reference, the voltage can be usually obtained with
a dedicated ADC API call, so there is no need to use this property
in that case, but for other references this property can be useful.

Acquisition time.
Use the ADC_ACQ_TIME macro to compose the value for this property
or pass ADC_ACQ_TIME_DEFAULT to use the default setting for a given
hardware (e.g. when the hardware does not allow to configure the
acquisition time).

When set, selects differential input mode for the channel. Otherwise,
single-ended mode is used unless the zephyr,input-negative property is
specified, in which case the differential mode is selected implicitly.

Positive ADC input. Used only for drivers that select
the ADC_CONFIGURABLE_INPUTS Kconfig option.

Negative ADC input. Used only for drivers that select
When specified, implies the differential input mode for the channel.

Oversampling setting to be used for the channel.
When specified, each sample is averaged from 2^N conversion results
(where N is the provided value).

Output pin selection for the current sources. The actual
interpretation depends on the driver. This is used only for drivers
which select the ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN
Kconfig option.

Output pin selection for the bias voltage. The actual interpretation
depends on the driver. This is used only for drivers which select
the ADC_CONFIGURABLE_VBIAS_PIN Kconfig option.

Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off.

Valid values are 1 or any even number from 2 to 14 for ESP32 and 2 to 490 for newer
Espressif MCUs like ESP32-C3.

Deprecated. This property has been renamed to bitrate.

Initial bitrate in bit/s. If this is unset, the initial bitrate is set to
CONFIG_CAN_DEFAULT_BITRATE.

Initial sample point in per mille (e.g. 875 equals 87.5%).

If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for
bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other
bitrates.

Actively controlled CAN transceiver.

Example:
  transceiver0: can-phy0 {
    compatible = "nxp,tja1040", "can-transceiver-gpio";
    standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
    max-bitrate = <1000000>;
    #phy-cells = <0>;
  };

  &can0 {
    status = "okay";

    phys = <&transceiver0>;
  };

Passive CAN transceiver. The child node must be named "can-transceiver".

Example:
  &can0 {

    can-transceiver {
      max-bitrate = <1000000>;
    };
  };

The minimum bitrate supported by the CAN transceiver in bits/s.

The maximum bitrate supported by the CAN transceiver in bits/s.

ESP32 LCD-CAM controller

The LCD-CAM controller consists of two functional modules: an LCD output block
and a DVP camera input block. Both modules share the same clock and pinctrl
resources.

Clock frequency of the SCL signal of the MBI-DBI peripheral, in Hz

Value of the GHWCFG1 register. It is used to determine available endpoint
types during driver pre-initialization.

Value of the GHWCFG2 register. It is used to determine available endpoint

Value of the GHWCFG4 register. It is used to determine available endpoint

ESP32 general-purpose timers.

Each Timer is part of a Timer Group and the number of available Timers
is SoC-dependent.

As as example, ESP32 has 4 Timers available, which are split in two
different groups (TIM0_G0, TIM1_G0, TIM0_G1 and TIM1_G1).

In order to use one of the available timers on your application add
a <board>.overlay file with contents as below

  &timer0 {
          status = "okay";
          prescaler = <10>;
  };

From the above, setting 'status' is required while the prescaler is
optional. Check below for more information on the prescaler.

The prescaler value defines the factor by which the APB clock will be
divided. The outcome of which serves as clock reference to the Timer
itself.

The allowed values for this property are in the range [2..65535].
Values above that range will be 16-bit-masked. Values 0 and 1 will be
forced to 2.

ESP32 watchdog.

ESP32 contains 3x Watchdog timers, 2x Main System Watchdog
Timer (MWDT), 1x RTC Watchdog Timer (RWDT). RWDT is not supported yet.

ESP32 TRNG (True Random Number Generator).

The TRNG uses the noise in the Wi-Fi/BT RF system. When Wi-Fi and BT are
disabled, the random number generator will give out pseudo-random numbers.

ESP32 LED Control (LEDC)

The LEDC controller is primarily designed to control the intensity of LEDs, although it can be
used to generate PWM signals for other purposes as well.

The mapping between the channel and GPIO is done through pinctrl

  &ledc0 {
    pinctrl-0 = <&ledc0_default>;
    pinctrl-names = "default";
  }

The 'ledc0_default' node state is defined in <board>-pinctrl.dtsi.

  ledc0_default: ledc0_default {
          group1 {
                  pinmux = <LEDC_CH0_GPIO0>,
                           <LEDC_CH1_GPIO2>,
                           <LEDC_CH2_GPIO4>;
                  output-enable;
          };
  };

If another GPIO mapping is desired, check if <board>-pinctrl.dtsi already have it defined,
otherwise, define the required mapping at your own application folder into a custom
<board>.overlay file.
The 'pinmux' property uses a macro defined in
https://github.com/zephyrproject-rtos/hal_espressif/tree/zephyr/include/dt-bindings/pinctrl
Before including a new node, check if the desired mapping is available according to the SoC.

As an example, the 'ledc0_custom' state below illustrates an alternate mapping using another set
of channels and pins in a custom overlay file.

  &pinctrl {

          ledc0_custom:  ledc0_custom {
                  group1 {
                          pinmux = <LEDC_CH0_GPIO0>,
                                   <LEDC_CH9_GPIO2>,
                                   <LEDC_CH10_GPIO4>;
                          output-enable;
                  };
           };

  };

Use the child bindings to configure the desired channel:

  &ledc0 {
    pinctrl-0 = <&ledc0_custom>;
    channel0@0 {
      reg = <0x0>;
      timer = <0>;
    };
    channel9@9 {
      reg = <0x9>;
      inverted;
    };
    channel10@a {
      reg = <0xa>;
      timer = <1>;
    };
  };

  For the channel to be initially inverted after the driver's init, the flag 'inverted' can
  be declared, as shown above for channel 9.

  Note: The channel's 'reg' property defines the ID of the channel. It must match the channel used
    in the 'pinmux'.

The ESP32 has 8 low speed channel and 8 high speed channels.
The low speed channel are mapped from channel 0 to 7, and the high speed are mapped from
channel 8 to 15.

High speed channels are only available in the ESP32 SoC. ESP32S2 and ESP32S3 have 8
available channels, and ESP32C3 has 6. In these SoCs there is no differentiation between
low or high speed.

Timer selection.
For maximum flexibility, the high-speed as well as the low-speed channels can be driven from
one of four high-speed/low-speed timers.

Initial channel output level.
This flag defines if the channel will remain initially inverted after driver init,
as any pwm_set() operation will re-evaluate if the output is inverted or not
according to the flag passed as parameter.

ESP32 Motor Control Pulse Width Modulator (MCPWM)

The MCPWM peripheral is intended for motor and power control.
It provides six PWM outputs that can be set up to operate in several topologies

ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1

Each MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators,
and a capture module.

Every PWM operator has two PWM outputs: PWMxA and PWMxB. They can work independently, in symmetric
and asymmetric configuration. MCPWMxA and MCPWMxB will share the same timer, thus having the same
operating frequency.

The driver currently always use the timer x for operator x. Timer 0 will use operator 0 for
PWM0A/B.
Timer 1 will use operator 1 for PWM1A/B, and so on.

Mapping channel ID:
Channel 0 -> Timer 0, Operator 0, output PWM0A
Channel 1 -> Timer 0, Operator 0, output PWM0B
Channel 2 -> Timer 1, Operator 1, output PWM1A
Channel 3 -> Timer 1, Operator 1, output PWM1B
Channel 4 -> Timer 2, Operator 2, output PWM2A
Channel 5 -> Timer 2, Operator 2, output PWM2B
Channel 6 -> Capture 0
Channel 7 -> Capture 1
Channel 8 -> Capture 2

Example: Use PWM0A output and capture 0:

pwm_loopback_0 {
  compatible = "test-pwm-loopback";
  pwms = <&mcpwm0 0 0 PWM_POLARITY_NORMAL>, #Channel 0 -> Output PWM0A
         <&mcpwm0 6 0 PWM_POLARITY_NORMAL>; #Channel 6 -> Capture 0;
};

The mapping between the output PWMxA/B or CaptureX and GPIO is done through pinctrl:

  &mcpwm0 {
    pinctrl-0 = <&mcpwm0_default>;
  }

The 'mcpwm0_default' node is defined inside the pinctrl node.

  &pinctrl {
    mcpwm0_default: mcpwm0_default {
      group1 {
        pinmux = <MCPWM0_OUT0A_GPIO0>,
          <MCPWM0_OUT0B_GPIO2>,
          <MCPWM0_OUT1A_GPIO4>;
        output-enable;
      };
      group2 {
        pinmux = <MCPWM0_CAP0_GPIO5>;
      };
    };
  };

Note: Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.

Use the prescale-timerX property to configure the timers:

  &mcpwm0 {
    prescale = <255>;
    prescale-timer0 = <103>;
    prescale-timer1 = <0>;
    prescale-timer2 = <255>;
  };

8 bit timer prescale for the global clock.
Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1).

8 bit timer prescale for timer 0.
Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1).

8 bit timer prescale for timer 1.
Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1).

8 bit timer prescale for timer 2.
Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1).

ESP32 Pulse Counter (PCNT)

The pulse counter module is designed to count the number of
rising and/or falling edges of an input signal.

The ESP32's PCNT module has 8 independent counting "units" numbered from 0 to 7.
ESP32S2 and ESP32S3 have 4 independent counting "units" numbered from 0 to 3.

Each pulse counter unit has a 16-bit signed counter register.

Each unit has two independent channel: ch0 and ch1 that can be configured
to either increment or decrement the counter.

Each channel has two inputs: a signal input that accepts signal edges
to be detected, as well as a control input that can be used to enable
or disable the signal input.

Each pulse counter unit also features a filter on each of the four inputs,
adding the option to ignore short glitches in the signals.

By combining the usage of both signal and control inputs, a PCNT unit can
act as a quadrature decoder.

The mapping between signal and control input and the pin is done through pinctrl.
Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.

The PCNT unit index.
The ESP32 has 8 PCNT units. ESP32S2/S3 have 4 PCNT units.

Define what to do on the positive edge of pulse input.
0 (Default) - Inhibit counter (counter value will not change in this condition).
1 - Increase counter value.
2 - Decrease counter value.

Define what to do on the negative edge of pulse input.

Define what to do when the control input is high.
0 (Default) - Don't change counter mode.
1 - Invert counter mode(increase -> decrease, decrease -> increase).
2 - Control mode: Inhibit counter (counter value will not change in this condition).

Define what to do when the control input is low.

/* Use PCNT to read a rotary-encoder */
&pinctrl {
    pcnt_default: pcnt_default {
        group1 {
            pinmux = <PCNT0_CH0SIG_GPIO14>,
                    <PCNT0_CH0CTRL_GPIO15>;
            bias-pull-up;
        };
    };
};
&pcnt {
  pinctrl-0 = <&pcnt_default>;
  pinctrl-names = "default";
  unit0@0 {
    reg = <0>;
    filter = <100>;
    channelA@0 {
        reg = <0>;
        sig-pos-mode = <2>;
        sig-neg-mode = <1>;
        ctrl-h-mode = <0>;
        ctrl-l-mode = <1>;
    };
  };
};

Clock pin for ESP32 and SoC models with fixed pins for SDIO.
For devices with GPIO matrix support, configuration shall be done
using pin control (pinctrl-0 field).

Command pin for ESP32 and SoC models with fixed pins for SDIO.

Data 0 pin for ESP32 and SoC models with fixed pins for SDIO.

Data 1 pin for ESP32 and SoC models with fixed pins for SDIO.

Data 2 pin for ESP32 and SoC models with fixed pins for SDIO.

Data 3 pin for ESP32 and SoC models with fixed pins for SDIO.

Power pin
This is a configurable pin to deliver power supply to the SD card.
It is configured as a GPIO in order to execute power toggles and
reinitialize the SD slave when necessary.

Max drive current in mA at 3.3V. A value of zero indicates no maximum
is specified by the driver.

Max drive current in mA at 3.0V. A value of zero indicates no maximum

Max drive current in mA at 1.8V. A value of zero indicates no maximum

Maximum bus frequency for SD card. This should be the highest frequency
the SDHC is capable of negotiating with cards on the bus.

Minimum bus frequency for SD card. This should be the frequency that
cards first will select when attached to the SDHC bus

time in ms for SDHC to delay when toggling power to the SD card. This
delay gives the card time to power up or down fully

Espressif ESP32 family AES Hardware Accelerator

The AES peripheral provides hardware acceleration for AES encryption
and decryption operations. It supports:
- ECB, CBC, CTR modes (SoC dependent)
- 128, 192, 256-bit key lengths
- XTS mode on selected SoCs (S2, S3, C3, C6, H2)

Defines the CPU clock source, each corresponding to different frequencies:
- 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
- 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
320 MHz or 480 MHz.
- 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
frequency of 17.5 MHz. 8 MHz for ESP32S2.
- 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)

Minimum residency duration in microseconds.

How much time the residency in a given idle state must last for state entry
to be worthwhile energywise. It includes the time to enter into this state
and represents the "break-even" time to justify the time and power spent
on the work needed for entering and exiting the state based on how much actual energy
is saved once in the state, compared to choosing the next shallowest state.

Worst case latency in microseconds required to exit the idle state.

Disable system managed device power management for this state. When set,
the power management subsystem will not suspend devices before entering
this state.

ESP32 pin controller

Espressif's pin controller is in charge of controlling pin configurations, pin
functionalities and pin properties as defined by pin states. In its turn, pin
states are composed by groups of pre-defined pin muxing definitions and user
provided pin properties.

Each Zephyr-based application has its own set of pin muxing/pin configuration
requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
could change a node's pin state properties. Though based on a particular board,
the same steps can be tweaked to address specifics of any other target board.

Suppose an application running on top of the ESP-WROVER-KIT board, for some
reason it needs I2C_0's SDA signal to be routed to GPIO_33. When looking at
that board's original device tree source file (i.e., 'esp_wrover_kit.dts'),
you'll notice that the I2C_0 node is already assigned to a pre-defined state.
Below is highlighted the information that most interests us on that file

    #include "esp_wrover_kit-pinctrl.dtsi"

    &i2c0 {
            ...
            pinctrl-0 = <&i2c0_default>;
            pinctrl-names = "default";
    };

From the above excerpt, the pincrl-0 property is assigned the 'i2c0_default'
state value. This and other pin states of the board are defined on another file
(in this case, 'esp_wrover_kit-pinctrl.dtsi') on the same folder of the DTS file.
Check below the excerpt describing I2C_0's default state on that file

    i2c0_default: i2c0_default {
            group1 {
                    pinmux = <I2C0_SDA_GPIO21>,
                             <I2C0_SCL_GPIO22>;
                    bias-pull-up;
                    drive-open-drain;
                    output-high;
            };
    };

Only the 'pinmux' property above is actually required, other properties can
be chosen if meaningful for the target application and, of course, supported
by your target hardware. For example, some custom board may have an external
pull-up resistor soldered to GPIO_21's pin pad, in which case, 'bias-pull-up'
could be no longer required.

Back to our fictional application, the previous I2C_0 state definition does not
meet our expectations as we would like to route I2C_0's SDA signal to GPIO_33
instead of to GPIO_21. To achieve it, we need to update the 'pinmux' property
accordingly.

Note that replacing 'I2C0_SDA_GPIO21' by 'I2C0_SDA_GPIO33' is very tempting and
may even work, however, unless you have checked the hardware documentation first,
it is not recommended. That's because there are no guarantees that a particular
IO pin has the capability to route any specific signal.

The recommendation is to check the pinmux macros definitions available for the
target SoC in the following URL

https://github.com/zephyrproject-rtos/zephyr/tree/main/include/zephyr/dt-bindings/pinctrl

The ESP-WROVER-KIT board is based on the ESP32 SoC, in that case, we search
through the file 'esp32-pinctrl.h' in the above URL. Luckily for us, there is
one definition on that file that corresponds to our needs

    #define I2C0_SDA_GPIO33 \
            ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)

Now, we go back to edit 'esp_wrover_kit-pinctrl.dtsi' and create a new pin state
on that file (or replace/update the one already defined) using the pinmux macro
definition above, yielding

            group1 {
                    pinmux = <I2C0_SDA_GPIO33>,
            };
    };

With proper modifications, the same steps above apply when using different
combinations of boards, SoCs, peripherals and peripheral pins.

Note: Not all pins are available for a given peripheral, it depends if that
      pin supports a set of properties required by the target peripheral.

      When defining a state, the pin muxing information is constrained to
      the definitions at 'hal_espressif', however, pin properties (like
      bias-push-pull, drive-open-drain, etc) can be freely chosen, given the
      property is meaningful to the peripheral signal and that it is also
      available in the target GPIO.

      Another thing worth noting is that all pin properties should be grouped.
      All pins sharing common properties go under a common group (in the above
      example, all pins are in 'group1'). Other peripherals can have more than
      one group.

Another useful pin property is 'sleep-hold-en'. When this property is
defined, the ESP GPIO pad hold feature is enabled for that pin during
system sleep. The pin state is latched right before the system enters
a low power mode and remains unchanged while the system is sleeping.
This ensures the GPIO level is retained even if the peripheral
controlling the pin is powered down or its registers lose state.

This property works in both input and output modes and is only
applicable to output-capable GPIOs.

Note: For deep sleep cycles, the automatic hold functionality may not
      cover the entire period from entering sleep until the application
      resumes execution. During deep sleep, register states are lost due to
      reset, and the hold configuration will be released during the driver
      initialization phase. For outputs where maintaining a stable level is
      critical (for example, edge-sensitive signals), the application may
      need to explicitly enable the hold feature using gpio_hold_en() before
      requesting a power-off. This ensures that the pin state remains held
      throughout the deep sleep period and until the application is running
      again.

ledc0_default: ledc0_default {
    group1 {
        pinmux = <LEDC_CH0_GPIO2>;
        sleep-hold-en;
    };
};

GPIO pins exposed on Seeeduino Xiao (and compatible devices) headers.

The Seeeeduino Xiao layout provides two headers, along opposite
edges of the board.

Proceeding counter-clockwise:
* A 7-pin Digital/Analog Input header.  This has input signals
  labeled from 0 at the top through 6 at the bottom.
* A 7-pin header Power and Digital/Analog Input header.  This
  has three power pins, followed by four inputs labeled 10 at the
  top through 7 at the bottom.

This binding provides a nexus mapping for 11 pins where parent pins 0
through 10 correspond to D0 through D10, as depicted below:

    0 D0 (A0/DAC)                5V   -
    1 D1 (A1)                    GND  -
    2 D2 (A2)                    3V3  -
    3 D3 (A3/CS0n)   (MOSI0/A10) D10 10
    4 D4 (A4/SDA0)    (MISO0/A9) D9   9
    5 D5 (A5/SCL0)     (SCK0/A8) D8   8
    6 D6 (A6/TX0)  (RX0/CS0n/A7) D7   7

https://github.com/Seeed-Studio/OSHW-XIAO-Series

Group of GPIO-controlled LEDs.

Each LED is defined in a child node of the gpio-leds node.

Human readable string describing the LED. It can be used by an
application to identify this LED or to retrieve its number/index
(i.e. child node number) on the parent device.

/ {
  leds {
    compatible = "gpio-leds";
    /*
     * led_0 is pin 1 on gpio0.
     * The LED is on when the pin is low, and off when the pin is high.
     */
    led_0 {
      gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
    };
    /*
     * led_1 is pin 2 on gpio0.
     * The LED is on when the pin is high, and off when it is low.
     */
    led_1 {
      gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
    };
    /*
     * led_2 is pin 15 on gpio1.
     * The LED is on when the pin is low, and the pin's internal pull-up resistor should be
     * enabled.
     */
    led_2 {
      gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
    };
  };
};

QEMU, a generic and open source machine emulator and virtualizer

Antmicro's open source simulation and virtual development framework

Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)

Virtual I/O Device Specification, developed by the OASIS consortium

A stand-in for a real vendor which can be used in examples and tests