Files
loramodem/build/zephyr_modules.txt
maze 45d1364a71 Add XIAO Wio-SX1262 overlay; support SX12xx bandwidths (including 62.5 kHz) as default
- boards/seeed/xiao_wio_sx1262: add overlay, .conf, board.yml
- app: support full set of SX12xx bandwidths; default BW set to 62 (62.5 kHz)
- Update Kconfig and prj.conf
- Update lora_modem.h/c for validation and mapping
2026-03-26 13:01:47 +01:00

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"acpica":"/Users/wijnand/zephyrproject/modules/lib/acpica":"${ZEPHYR_ACPICA_CMAKE_DIR}"
"cmsis":"/Users/wijnand/zephyrproject/modules/hal/cmsis":"${ZEPHYR_CMSIS_CMAKE_DIR}"
"cmsis-dsp":"/Users/wijnand/zephyrproject/modules/lib/cmsis-dsp":"${ZEPHYR_CMSIS_DSP_CMAKE_DIR}"
"cmsis-nn":"/Users/wijnand/zephyrproject/modules/lib/cmsis-nn":"${ZEPHYR_CMSIS_NN_CMAKE_DIR}"
"cmsis_6":"/Users/wijnand/zephyrproject/modules/hal/cmsis_6":"${ZEPHYR_CMSIS_6_CMAKE_DIR}"
"dhara":"/Users/wijnand/zephyrproject/modules/lib/dhara":"${ZEPHYR_DHARA_CMAKE_DIR}"
"fatfs":"/Users/wijnand/zephyrproject/modules/fs/fatfs":"${ZEPHYR_FATFS_CMAKE_DIR}"
"adi":"/Users/wijnand/zephyrproject/modules/hal/adi":"/Users/wijnand/zephyrproject/modules/hal/adi"
"hal_afbr":"/Users/wijnand/zephyrproject/modules/hal/afbr":"${ZEPHYR_HAL_AFBR_CMAKE_DIR}"
"hal_ambiq":"/Users/wijnand/zephyrproject/modules/hal/ambiq":"/Users/wijnand/zephyrproject/modules/hal/ambiq"
"atmel":"/Users/wijnand/zephyrproject/modules/hal/atmel":"/Users/wijnand/zephyrproject/modules/hal/atmel"
"hal_bouffalolab":"/Users/wijnand/zephyrproject/modules/hal/bouffalolab":"${ZEPHYR_HAL_BOUFFALOLAB_CMAKE_DIR}"
"hal_espressif":"/Users/wijnand/zephyrproject/modules/hal/espressif":"${ZEPHYR_HAL_ESPRESSIF_CMAKE_DIR}"
"hal_ethos_u":"/Users/wijnand/zephyrproject/modules/hal/ethos_u":"${ZEPHYR_HAL_ETHOS_U_CMAKE_DIR}"
"hal_gigadevice":"/Users/wijnand/zephyrproject/modules/hal/gigadevice":"${ZEPHYR_HAL_GIGADEVICE_CMAKE_DIR}"
"hal_infineon":"/Users/wijnand/zephyrproject/modules/hal/infineon":"${ZEPHYR_HAL_INFINEON_CMAKE_DIR}"
"hal_intel":"/Users/wijnand/zephyrproject/modules/hal/intel":"/Users/wijnand/zephyrproject/modules/hal/intel/zephyr"
"microchip":"/Users/wijnand/zephyrproject/modules/hal/microchip":"/Users/wijnand/zephyrproject/modules/hal/microchip"
"hal_nordic":"/Users/wijnand/zephyrproject/modules/hal/nordic":"${ZEPHYR_HAL_NORDIC_CMAKE_DIR}"
"nuvoton":"/Users/wijnand/zephyrproject/modules/hal/nuvoton":"/Users/wijnand/zephyrproject/modules/hal/nuvoton"
"hal_nxp":"/Users/wijnand/zephyrproject/modules/hal/nxp":"${ZEPHYR_HAL_NXP_CMAKE_DIR}"
"openisa":"/Users/wijnand/zephyrproject/modules/hal/openisa":"/Users/wijnand/zephyrproject/modules/hal/openisa"
"quicklogic":"/Users/wijnand/zephyrproject/modules/hal/quicklogic":"/Users/wijnand/zephyrproject/modules/hal/quicklogic"
"hal_realtek":"/Users/wijnand/zephyrproject/modules/hal/realtek":"${ZEPHYR_HAL_REALTEK_CMAKE_DIR}"
"hal_renesas":"/Users/wijnand/zephyrproject/modules/hal/renesas":"/Users/wijnand/zephyrproject/modules/hal/renesas"
"hal_rpi_pico":"/Users/wijnand/zephyrproject/modules/hal/rpi_pico":"${ZEPHYR_HAL_RPI_PICO_CMAKE_DIR}"
"hal_sifli":"/Users/wijnand/zephyrproject/modules/hal/sifli":"${ZEPHYR_HAL_SIFLI_CMAKE_DIR}"
"hal_silabs":"/Users/wijnand/zephyrproject/modules/hal/silabs":"${ZEPHYR_HAL_SILABS_CMAKE_DIR}"
"hal_st":"/Users/wijnand/zephyrproject/modules/hal/st":"/Users/wijnand/zephyrproject/modules/hal/st"
"hal_stm32":"/Users/wijnand/zephyrproject/modules/hal/stm32":"/Users/wijnand/zephyrproject/modules/hal/stm32"
"hal_tdk":"/Users/wijnand/zephyrproject/modules/hal/tdk":"/Users/wijnand/zephyrproject/modules/hal/tdk"
"hal_telink":"/Users/wijnand/zephyrproject/modules/hal/telink":"/Users/wijnand/zephyrproject/modules/hal/telink"
"ti":"/Users/wijnand/zephyrproject/modules/hal/ti":"/Users/wijnand/zephyrproject/modules/hal/ti"
"hal_wch":"/Users/wijnand/zephyrproject/modules/hal/wch":"${ZEPHYR_HAL_WCH_CMAKE_DIR}"
"hal_wurthelektronik":"/Users/wijnand/zephyrproject/modules/hal/wurthelektronik":"/Users/wijnand/zephyrproject/modules/hal/wurthelektronik"
"xtensa":"/Users/wijnand/zephyrproject/modules/hal/xtensa":"/Users/wijnand/zephyrproject/modules/hal/xtensa"
"hostap":"/Users/wijnand/zephyrproject/modules/lib/hostap":"${ZEPHYR_HOSTAP_CMAKE_DIR}"
"liblc3":"/Users/wijnand/zephyrproject/modules/lib/liblc3":"${ZEPHYR_LIBLC3_CMAKE_DIR}"
"libmctp":"/Users/wijnand/zephyrproject/modules/lib/libmctp":"/Users/wijnand/zephyrproject/modules/lib/libmctp/zephyr"
"libmetal":"/Users/wijnand/zephyrproject/modules/hal/libmetal":"/Users/wijnand/zephyrproject/modules/hal/libmetal"
"libsbc":"/Users/wijnand/zephyrproject/modules/lib/libsbc":"${ZEPHYR_LIBSBC_CMAKE_DIR}"
"littlefs":"/Users/wijnand/zephyrproject/modules/fs/littlefs":"${ZEPHYR_LITTLEFS_CMAKE_DIR}"
"lora-basics-modem":"/Users/wijnand/zephyrproject/modules/lib/lora-basics-modem":"${ZEPHYR_LORA_BASICS_MODEM_CMAKE_DIR}"
"loramac-node":"/Users/wijnand/zephyrproject/modules/lib/loramac-node":"${ZEPHYR_LORAMAC_NODE_CMAKE_DIR}"
"lvgl":"/Users/wijnand/zephyrproject/modules/lib/gui/lvgl":"${ZEPHYR_LVGL_CMAKE_DIR}"
"mbedtls":"/Users/wijnand/zephyrproject/modules/crypto/mbedtls":"${ZEPHYR_MBEDTLS_CMAKE_DIR}"
"mbedtls-3.6":"/Users/wijnand/zephyrproject/modules/crypto/mbedtls-3.6":""
"mcuboot":"/Users/wijnand/zephyrproject/bootloader/mcuboot":"/Users/wijnand/zephyrproject/bootloader/mcuboot/boot/bootutil/zephyr"
"mipi-sys-t":"/Users/wijnand/zephyrproject/modules/debug/mipi-sys-t":"/Users/wijnand/zephyrproject/modules/debug/mipi-sys-t"
"nanopb":"/Users/wijnand/zephyrproject/modules/lib/nanopb":"${ZEPHYR_NANOPB_CMAKE_DIR}"
"nrf_wifi":"/Users/wijnand/zephyrproject/modules/lib/nrf_wifi":"${ZEPHYR_NRF_WIFI_CMAKE_DIR}"
"open-amp":"/Users/wijnand/zephyrproject/modules/lib/open-amp":"/Users/wijnand/zephyrproject/modules/lib/open-amp"
"openthread":"/Users/wijnand/zephyrproject/modules/lib/openthread":"${ZEPHYR_OPENTHREAD_CMAKE_DIR}"
"percepio":"/Users/wijnand/zephyrproject/modules/debug/percepio":"${ZEPHYR_PERCEPIO_CMAKE_DIR}"
"picolibc":"/Users/wijnand/zephyrproject/modules/lib/picolibc":"/Users/wijnand/zephyrproject/modules/lib/picolibc"
"psa-arch-tests":"/Users/wijnand/zephyrproject/modules/tee/tf-m/psa-arch-tests":""
"segger":"/Users/wijnand/zephyrproject/modules/debug/segger":"${ZEPHYR_SEGGER_CMAKE_DIR}"
"tf-m-tests":"/Users/wijnand/zephyrproject/modules/tee/tf-m/tf-m-tests":""
"tf-psa-crypto":"/Users/wijnand/zephyrproject/modules/crypto/mbedtls/tf-psa-crypto":""
"trusted-firmware-a":"/Users/wijnand/zephyrproject/modules/tee/tf-a/trusted-firmware-a":"${ZEPHYR_TRUSTED_FIRMWARE_A_CMAKE_DIR}"
"trusted-firmware-m":"/Users/wijnand/zephyrproject/modules/tee/tf-m/trusted-firmware-m":"${ZEPHYR_TRUSTED_FIRMWARE_M_CMAKE_DIR}"
"uoscore-uedhoc":"/Users/wijnand/zephyrproject/modules/lib/uoscore-uedhoc":"${ZEPHYR_UOSCORE_UEDHOC_CMAKE_DIR}"
"zcbor":"/Users/wijnand/zephyrproject/modules/lib/zcbor":"${ZEPHYR_ZCBOR_CMAKE_DIR}"
"nrf_hw_models":"/Users/wijnand/zephyrproject/modules/bsim_hw_models/nrf_hw_models":"/Users/wijnand/zephyrproject/modules/bsim_hw_models/nrf_hw_models"