123 lines
4.0 KiB
C
123 lines
4.0 KiB
C
/* Copyright 2018 Jack Humbert
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* Copyright 2018 Yiancar
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This library is only valid for STM32 processors.
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* This library follows the convention of the AVR i2c_master library.
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* As a result addresses are expected to be already shifted (addr << 1).
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* I2CD1 is the default driver which corresponds to pins B6 and B7. This
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* can be changed.
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* Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
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* STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
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* but using any other I2C pins should be trivial.
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*/
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#include "i2c_master.h"
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#include "quantum.h"
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#include <string.h>
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#include <hal.h>
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static uint8_t i2c_address;
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// This configures the I2C clock to 400khz assuming a 72Mhz clock
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// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
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static const I2CConfig i2cconfig = {
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STM32_TIMINGR_PRESC(15U) |
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STM32_TIMINGR_SCLDEL(4U) | STM32_TIMINGR_SDADEL(2U) |
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STM32_TIMINGR_SCLH(15U) | STM32_TIMINGR_SCLL(21U),
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0,
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0
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};
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static i2c_status_t chibios_to_qmk(const msg_t* status) {
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switch (*status) {
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case I2C_NO_ERROR:
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return I2C_STATUS_SUCCESS;
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case I2C_TIMEOUT:
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return I2C_STATUS_TIMEOUT;
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// I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
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default:
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return I2C_STATUS_ERROR;
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}
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}
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__attribute__ ((weak))
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void i2c_init(void)
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{
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// Try releasing special pins for a short time
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palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_INPUT);
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palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_INPUT);
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chThdSleepMilliseconds(10);
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palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
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palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
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//i2cInit(); //This is invoked by halInit() so no need to redo it.
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}
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i2c_status_t i2c_start(uint8_t address)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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return I2C_STATUS_SUCCESS;
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}
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = address;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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uint8_t complete_packet[length + 1];
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for(uint8_t i = 0; i < length; i++)
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{
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complete_packet[i+1] = data[i];
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}
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complete_packet[0] = regaddr;
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t* regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
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{
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i2c_address = devaddr;
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i2cStart(&I2C_DRIVER, &i2cconfig);
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msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), regaddr, 1, data, length, MS2ST(timeout));
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return chibios_to_qmk(&status);
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}
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void i2c_stop(void)
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{
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i2cStop(&I2C_DRIVER);
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}
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