530 lines
18 KiB
C++
530 lines
18 KiB
C++
/* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
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This software may be distributed and modified under the terms of the GNU
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General Public License version 2 (GPL2) as published by the Free Software
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Foundation and appearing in the file GPL2.TXT included in the packaging of
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this file. Please note that GPL2 Section 2[b] requires that all works based
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on this software must also be made publicly available under the terms of
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the GPL2 ("Copyleft").
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Contact information
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-------------------
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Circuits At Home, LTD
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Web : http://www.circuitsathome.com
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e-mail : support@circuitsathome.com
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*/
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/* MAX3421E-based USB Host Library header file */
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#if !defined(_usb_h_) || defined(_USBHOST_H_)
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#error "Never include usbhost.h directly; include Usb.h instead"
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#else
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#define _USBHOST_H_
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#if USING_SPI4TEENSY3
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#include <spi4teensy3.h>
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#include <sys/types.h>
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#endif
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/* SPI initialization */
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template< typename SPI_CLK, typename SPI_MOSI, typename SPI_MISO, typename SPI_SS > class SPi {
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public:
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#if USING_SPI4TEENSY3
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static void init() {
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// spi4teensy3 inits everything for us, except /SS
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// CLK, MOSI and MISO are hard coded for now.
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// spi4teensy3::init(0,0,0); // full speed, cpol 0, cpha 0
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spi4teensy3::init(); // full speed, cpol 0, cpha 0
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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}
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#elif SPI_HAS_TRANSACTION
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static void init() {
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SPI.begin(); // The SPI library with transaction will take care of setting up the pins - settings is set in beginTransaction()
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}
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#elif !defined(SPDR)
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static void init() {
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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SPI.begin();
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#if defined(__MIPSEL__)
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SPI.setClockDivider(1);
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#elif defined(__ARDUINO_X86__)
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#ifdef SPI_CLOCK_1M // Hack used to check if setClockSpeed is available
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SPI.setClockSpeed(12000000); // The MAX3421E can handle up to 26MHz, but in practice this was the maximum that I could reliably use
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#else
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SPI.setClockDivider(SPI_CLOCK_DIV2); // This will set the SPI frequency to 8MHz - it could be higher, but it is not supported in the old API
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#endif
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#else
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SPI.setClockDivider(4); // Set speed to 84MHz/4=21MHz - the MAX3421E can handle up to 26MHz
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#endif
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}
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#elif defined(RBL_NRF51822)
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static void init() {
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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SPI.begin();
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// SPI.setFrequency(SPI_FREQUENCY_8M);
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}
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#else
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static void init() {
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//uint8_t tmp;
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SPI_CLK::SetDirWrite();
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SPI_MOSI::SetDirWrite();
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SPI_MISO::SetDirRead();
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SPI_SS::SetDirWrite();
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/* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
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SPCR = 0x50;
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SPSR = 0x01; // 0x01
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/**/
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//tmp = SPSR;
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//tmp = SPDR;
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}
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#endif
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};
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/* SPI pin definitions. see avrpins.h */
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#if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__) || defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
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typedef SPi< Pb1, Pb2, Pb3, Pb0 > spi;
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#elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
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typedef SPi< Pb5, Pb3, Pb4, Pb2 > spi;
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#elif defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)
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typedef SPi< Pb7, Pb5, Pb6, Pb4 > spi;
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#elif (defined(CORE_TEENSY) && (defined(__MK20DX128__) || defined(__MK20DX256__))) || defined(__ARDUINO_X86__) || defined(__MIPSEL__)
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typedef SPi< P13, P11, P12, P10 > spi;
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#elif defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)
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typedef SPi< P76, P75, P74, P10 > spi;
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#elif defined(RBL_NRF51822)
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typedef SPi< P16, P18, P17, P10 > spi;
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#else
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#error "No SPI entry in usbhost.h"
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#endif
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typedef enum {
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vbus_on = 0,
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vbus_off = GPX_VBDET
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} VBUS_t;
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template< typename SPI_SS, typename INTR > class MAX3421e /* : public spi */ {
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static uint8_t vbusState;
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public:
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MAX3421e();
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void regWr(uint8_t reg, uint8_t data);
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uint8_t* bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p);
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void gpioWr(uint8_t data);
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uint8_t regRd(uint8_t reg);
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uint8_t* bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p);
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uint8_t gpioRd();
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uint16_t reset();
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int8_t Init();
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int8_t Init(int mseconds);
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void vbusPower(VBUS_t state) {
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regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL | state));
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}
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uint8_t getVbusState(void) {
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return vbusState;
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};
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void busprobe();
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uint8_t GpxHandler();
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uint8_t IntHandler();
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uint8_t Task();
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};
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::vbusState = 0;
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/* constructor */
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template< typename SPI_SS, typename INTR >
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MAX3421e< SPI_SS, INTR >::MAX3421e() {
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// Leaving ADK hardware setup in here, for now. This really belongs with the other parts.
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#ifdef BOARD_MEGA_ADK
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// For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH
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P55::SetDirWrite();
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P55::Set();
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#endif
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};
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/* write single byte into MAX3421 register */
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
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XMEM_ACQUIRE_SPI();
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#if SPI_HAS_TRANSACTION
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SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
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#endif
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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uint8_t c[2];
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c[0] = reg | 0x02;
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c[1] = data;
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spi4teensy3::send(c, 2);
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#elif SPI_HAS_TRANSACTION
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uint8_t c[2];
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c[0] = reg | 0x02;
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c[1] = data;
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SPI.transfer(c, 2);
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#elif !defined(SPDR)
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SPI.transfer(reg | 0x02);
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SPI.transfer(data);
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#else
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SPDR = (reg | 0x02);
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while(!(SPSR & (1 << SPIF)));
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SPDR = data;
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while(!(SPSR & (1 << SPIF)));
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#endif
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SPI_SS::Set();
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#if SPI_HAS_TRANSACTION
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SPI.endTransaction();
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#endif
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XMEM_RELEASE_SPI();
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return;
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};
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/* multiple-byte write */
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/* returns a pointer to memory position after last written */
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template< typename SPI_SS, typename INTR >
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uint8_t* MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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XMEM_ACQUIRE_SPI();
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#if SPI_HAS_TRANSACTION
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SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
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#endif
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg | 0x02);
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spi4teensy3::send(data_p, nbytes);
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data_p += nbytes;
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#elif SPI_HAS_TRANSACTION
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SPI.transfer(reg | 0x02);
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SPI.transfer(data_p, nbytes);
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data_p += nbytes;
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#elif defined(__ARDUINO_X86__)
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SPI.transfer(reg | 0x02);
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SPI.transferBuffer(data_p, NULL, nbytes);
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data_p += nbytes;
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#elif !defined(SPDR)
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SPI.transfer(reg | 0x02);
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while(nbytes) {
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SPI.transfer(*data_p);
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nbytes--;
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data_p++; // advance data pointer
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}
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#else
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SPDR = (reg | 0x02); //set WR bit and send register number
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while(nbytes) {
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while(!(SPSR & (1 << SPIF))); //check if previous byte was sent
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SPDR = (*data_p); // send next data byte
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nbytes--;
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data_p++; // advance data pointer
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}
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while(!(SPSR & (1 << SPIF)));
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#endif
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SPI_SS::Set();
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#if SPI_HAS_TRANSACTION
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SPI.endTransaction();
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#endif
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XMEM_RELEASE_SPI();
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return ( data_p);
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}
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/* GPIO write */
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/*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
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/* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::gpioWr(uint8_t data) {
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regWr(rIOPINS1, data);
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data >>= 4;
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regWr(rIOPINS2, data);
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return;
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}
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/* single host register read */
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
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XMEM_ACQUIRE_SPI();
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#if SPI_HAS_TRANSACTION
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SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
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#endif
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg);
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uint8_t rv = spi4teensy3::receive();
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SPI_SS::Set();
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#elif !defined(SPDR) || SPI_HAS_TRANSACTION
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SPI.transfer(reg);
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uint8_t rv = SPI.transfer(0); // Send empty byte
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SPI_SS::Set();
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#else
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SPDR = reg;
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while(!(SPSR & (1 << SPIF)));
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SPDR = 0; // Send empty byte
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while(!(SPSR & (1 << SPIF)));
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SPI_SS::Set();
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uint8_t rv = SPDR;
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#endif
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#if SPI_HAS_TRANSACTION
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SPI.endTransaction();
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#endif
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XMEM_RELEASE_SPI();
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return (rv);
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}
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/* multiple-byte register read */
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/* returns a pointer to a memory position after last read */
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template< typename SPI_SS, typename INTR >
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uint8_t* MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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XMEM_ACQUIRE_SPI();
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#if SPI_HAS_TRANSACTION
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SPI.beginTransaction(SPISettings(26000000, MSBFIRST, SPI_MODE0)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
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#endif
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg);
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spi4teensy3::receive(data_p, nbytes);
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data_p += nbytes;
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#elif SPI_HAS_TRANSACTION
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SPI.transfer(reg);
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memset(data_p, 0, nbytes); // Make sure we send out empty bytes
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SPI.transfer(data_p, nbytes);
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data_p += nbytes;
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#elif defined(__ARDUINO_X86__)
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SPI.transfer(reg);
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SPI.transferBuffer(NULL, data_p, nbytes);
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data_p += nbytes;
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#elif !defined(SPDR)
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SPI.transfer(reg);
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while(nbytes) {
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*data_p++ = SPI.transfer(0);
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nbytes--;
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}
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#else
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SPDR = reg;
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while(!(SPSR & (1 << SPIF))); //wait
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while(nbytes) {
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SPDR = 0; // Send empty byte
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nbytes--;
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while(!(SPSR & (1 << SPIF)));
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#if 0
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{
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*data_p = SPDR;
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printf("%2.2x ", *data_p);
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}
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data_p++;
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}
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printf("\r\n");
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#else
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*data_p++ = SPDR;
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}
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#endif
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#endif
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SPI_SS::Set();
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#if SPI_HAS_TRANSACTION
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SPI.endTransaction();
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#endif
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XMEM_RELEASE_SPI();
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return ( data_p);
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}
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/* GPIO read. See gpioWr for explanation */
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/* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::gpioRd() {
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uint8_t gpin = 0;
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gpin = regRd(rIOPINS2); //pins 4-7
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gpin &= 0xf0; //clean lower nibble
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gpin |= (regRd(rIOPINS1) >> 4); //shift low bits and OR with upper from previous operation.
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return ( gpin);
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}
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/* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
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or zero if PLL haven't stabilized in 65535 cycles */
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template< typename SPI_SS, typename INTR >
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uint16_t MAX3421e< SPI_SS, INTR >::reset() {
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uint16_t i = 0;
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regWr(rUSBCTL, bmCHIPRES);
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regWr(rUSBCTL, 0x00);
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while(++i) {
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if((regRd(rUSBIRQ) & bmOSCOKIRQ)) {
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break;
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}
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}
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return ( i);
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}
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/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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template< typename SPI_SS, typename INTR >
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int8_t MAX3421e< SPI_SS, INTR >::Init() {
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XMEM_ACQUIRE_SPI();
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// Moved here.
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// you really should not init hardware in the constructor when it involves locks.
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// Also avoids the vbus flicker issue confusing some devices.
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/* pin and peripheral setup */
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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spi::init();
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INTR::SetDirRead();
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XMEM_RELEASE_SPI();
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/* MAX3421E - full-duplex SPI, level interrupt */
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// GPX pin on. Moved here, otherwise we flicker the vbus.
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regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL));
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if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
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return ( -1);
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}
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regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST); // set pull-downs, Host
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regWr(rHIEN, bmCONDETIE | bmFRAMEIE); //connection detection
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/* check if device is connected */
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regWr(rHCTL, bmSAMPLEBUS); // sample USB bus
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while(!(regRd(rHCTL) & bmSAMPLEBUS)); //wait for sample operation to finish
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busprobe(); //check if anything is connected
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regWr(rHIRQ, bmCONDETIRQ); //clear connection detect interrupt
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regWr(rCPUCTL, 0x01); //enable interrupt pin
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return ( 0);
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}
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/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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template< typename SPI_SS, typename INTR >
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int8_t MAX3421e< SPI_SS, INTR >::Init(int mseconds) {
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XMEM_ACQUIRE_SPI();
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// Moved here.
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// you really should not init hardware in the constructor when it involves locks.
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// Also avoids the vbus flicker issue confusing some devices.
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/* pin and peripheral setup */
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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spi::init();
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INTR::SetDirRead();
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XMEM_RELEASE_SPI();
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/* MAX3421E - full-duplex SPI, level interrupt, vbus off */
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regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL | GPX_VBDET));
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if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
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return ( -1);
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}
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// Delay a minimum of 1 second to ensure any capacitors are drained.
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// 1 second is required to make sure we do not smoke a Microdrive!
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if(mseconds < 1000) mseconds = 1000;
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delay(mseconds);
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regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST); // set pull-downs, Host
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regWr(rHIEN, bmCONDETIE | bmFRAMEIE); //connection detection
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/* check if device is connected */
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regWr(rHCTL, bmSAMPLEBUS); // sample USB bus
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while(!(regRd(rHCTL) & bmSAMPLEBUS)); //wait for sample operation to finish
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busprobe(); //check if anything is connected
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regWr(rHIRQ, bmCONDETIRQ); //clear connection detect interrupt
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regWr(rCPUCTL, 0x01); //enable interrupt pin
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// GPX pin on. This is done here so that busprobe will fail if we have a switch connected.
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regWr(rPINCTL, (bmFDUPSPI | bmINTLEVEL));
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return ( 0);
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}
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/* probe bus to determine device presence and speed and switch host to this speed */
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::busprobe() {
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uint8_t bus_sample;
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bus_sample = regRd(rHRSL); //Get J,K status
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bus_sample &= (bmJSTATUS | bmKSTATUS); //zero the rest of the byte
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switch(bus_sample) { //start full-speed or low-speed host
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case( bmJSTATUS):
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if((regRd(rMODE) & bmLOWSPEED) == 0) {
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regWr(rMODE, MODE_FS_HOST); //start full-speed host
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vbusState = FSHOST;
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} else {
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regWr(rMODE, MODE_LS_HOST); //start low-speed host
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vbusState = LSHOST;
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}
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break;
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case( bmKSTATUS):
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if((regRd(rMODE) & bmLOWSPEED) == 0) {
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regWr(rMODE, MODE_LS_HOST); //start low-speed host
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vbusState = LSHOST;
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} else {
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regWr(rMODE, MODE_FS_HOST); //start full-speed host
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vbusState = FSHOST;
|
|
}
|
|
break;
|
|
case( bmSE1): //illegal state
|
|
vbusState = SE1;
|
|
break;
|
|
case( bmSE0): //disconnected state
|
|
regWr(rMODE, bmDPPULLDN | bmDMPULLDN | bmHOST | bmSEPIRQ);
|
|
vbusState = SE0;
|
|
break;
|
|
}//end switch( bus_sample )
|
|
}
|
|
|
|
/* MAX3421 state change task and interrupt handler */
|
|
template< typename SPI_SS, typename INTR >
|
|
uint8_t MAX3421e< SPI_SS, INTR >::Task(void) {
|
|
uint8_t rcode = 0;
|
|
uint8_t pinvalue;
|
|
//USB_HOST_SERIAL.print("Vbus state: ");
|
|
//USB_HOST_SERIAL.println( vbusState, HEX );
|
|
pinvalue = INTR::IsSet(); //Read();
|
|
//pinvalue = digitalRead( MAX_INT );
|
|
if(pinvalue == 0) {
|
|
rcode = IntHandler();
|
|
}
|
|
// pinvalue = digitalRead( MAX_GPX );
|
|
// if( pinvalue == LOW ) {
|
|
// GpxHandler();
|
|
// }
|
|
// usbSM(); //USB state machine
|
|
return ( rcode);
|
|
}
|
|
|
|
template< typename SPI_SS, typename INTR >
|
|
uint8_t MAX3421e< SPI_SS, INTR >::IntHandler() {
|
|
uint8_t HIRQ;
|
|
uint8_t HIRQ_sendback = 0x00;
|
|
HIRQ = regRd(rHIRQ); //determine interrupt source
|
|
//if( HIRQ & bmFRAMEIRQ ) { //->1ms SOF interrupt handler
|
|
// HIRQ_sendback |= bmFRAMEIRQ;
|
|
//}//end FRAMEIRQ handling
|
|
if(HIRQ & bmCONDETIRQ) {
|
|
busprobe();
|
|
HIRQ_sendback |= bmCONDETIRQ;
|
|
}
|
|
/* End HIRQ interrupts handling, clear serviced IRQs */
|
|
regWr(rHIRQ, HIRQ_sendback);
|
|
return ( HIRQ_sendback);
|
|
}
|
|
//template< typename SPI_SS, typename INTR >
|
|
//uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
|
|
//{
|
|
// uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
|
|
//// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
|
|
//// vbusPwr( OFF ); //attempt powercycle
|
|
//// delay( 1000 );
|
|
//// vbusPwr( ON );
|
|
//// regWr( rGPINIRQ, bmGPINIRQ7 );
|
|
//// }
|
|
// return( GPINIRQ );
|
|
//}
|
|
|
|
#endif // _USBHOST_H_
|