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/*
Copyright Jeroen Vreeken (jeroen@vreeken.net), 2014, 2015
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _INCLUDE_AM335X_
#define _INCLUDE_AM335X_
#include <inttypes.h>
#include <unistd.h>
#define AM335X_SYSCLK 100000000
#define AM335X_CM_BASE 0x44e00000
#define AM335X_CM_SIZE 0x00000b00
#define AM335X_CM_PER_BASE 0x44e00000
#define AM335X_CM_PER_SIZE 0x00000400
#define AM335X_CM_WKUP_BASE 0x44e00400
#define AM335X_CM_WKUP_SIZE 0x00000100
#define AM335X_CM_IDLEST_MASK 0x00030000
#define AM335X_CM_IDLEST_FUNCTIONAL 0x0
#define AM335X_CM_IDLEST_TRANSITION 0x1
#define AM335X_CM_IDLEST_IDLE 0x2
#define AM335X_CM_IDLEST_DISABLED 0x3
#define AM335X_CM_MODULEMODE_DISABLE 0x00000000
#define AM335X_CM_MODULEMODE_ENABLE 0x00000002
#define AM335X_CM_PER_L4LS_CLKCTRL 0x00000060
#define AM335X_CM_PER_GPIO1_CLKCTRL 0x000000ac
#define AM335X_CM_PER_GPIO2_CLKCTRL 0x000000b0
#define AM335X_CM_PER_GPIO3_CLKCTRL 0x000000b4
#define AM335X_CM_PER_EPWMSS1_CLKCTRL 0x000000cc
#define AM335X_CM_PER_EPWMSS0_CLKCTRL 0x000000d4
#define AM335X_CM_PER_EPWMSS2_CLKCTRL 0x000000d8
#define AM335X_CM_WKUP_ADC_TSC_CLKCTRL 0x000004bc
#define AM335X_ADC_BASE 0x44e0d000
#define AM335X_ADC_SIZE 0x00002000
#define AM335X_CONTROL_MODULE_BASE 0x44e10000
#define AM335X_CONTROL_MODULE_PINMUX_SLEWCTRL_FAST 0x00000000
#define AM335X_CONTROL_MODULE_PINMUX_SLEWCTRL_SLOW 0x00000040
#define AM335X_CONTROL_MODULE_PINMUX_RX 0x00000020
#define AM335X_CONTROL_MODULE_PINMUX_PU 0x00000010
#define AM335X_CONTROL_MODULE_PINMUX_PUEN 0x00000008
#define AM335X_CONTROL_MODULE_PINMUX_MODE_MASK 0x00000007
#define AM335X_CONTROL_MODULE_SIZE 0x00002000
#define AM335X_CONTROL_MODULE_CONF 0x800
#define AM335X_CONTROL_MODULE_CONF_GPMC_AD0 0x000
#define AM335X_CONTROL_MODULE_CONF_MCASP0_ACLKX 0x190 /* P9_31, 1: pwm0 A */
#define AM335X_CONTROL_MODULE_CONF_MCASP0_FSX 0x194 /* P9_29, 1: pwm0 B */
#define AM335X_CONTROL_MODULE_CONF_LCD_DATA0 0x0a0 /* P8_45, 3: pwm2 A */
#define AM335X_CONTROL_MODULE_CONF_LCD_DATA1 0x0a4 /* P8_46, 3: pwm2 B */
#define AM335X_CONTROL_MODULE_CONF_LCD_DATA10 0x0c8 /* P8_36, 2: pwm1 A */
#define AM335X_CONTROL_MODULE_CONF_LCD_DATA11 0x0cc /* P8_34, 2: pwm1 B */
#define AM335X_CONTROL_MODULE_PWMSS_CTRL 0x664
#define AM335X_CONTROL_MODULE_PWMSS0_TBCLKEN 0x00000001
#define AM335X_CONTROL_MODULE_PWMSS1_TBCLKEN 0x00000002
#define AM335X_CONTROL_MODULE_PWMSS2_TBCLKEN 0x00000004
#define AM335X_PWMSS0_BASE 0x48300000
#define AM335X_PWMSS1_BASE 0x48302000
#define AM335X_PWMSS2_BASE 0x48304000
#define AM335X_PWMSS_SIZE 0x00001000
#define AM335X_PWMSS_REG_IDVER 0x000
#define AM335X_PWMSS_IDVER_SCHEME_GET(x) (((x) & 0xc0000000) >> 30)
#define AM335X_PWMSS_IDVER_FUNC_GET(x) (((x) & 0x0fff0000) >> 16)
#define AM335X_PWMSS_IDVER_FUNC 0x740
#define AM335X_PWMSS_IDVER_X_MAJOR_GET(x) (((x) & 0x00000700) >> 8)
#define AM335X_PWMSS_IDVER_Y_MINOR_GET(x) (((x) & 0x0000001f) )
#define AM335X_PWMSS_REG_SYSCONFIG 0x004
#define AM335X_PWMSS_SYSCONFIG_IDLEMODE_SMART 0x00000008
#define AM335X_PWMSS_REG_CLKCONFIG 0x008
#define AM335X_PWMSS_CLKCONFIG_EPWMCLK_EN 0x00000100
#define AM335X_PWMSS_CLKCONFIG_EPWMCLKSTOP_REQ 0x00000200
#define AM335X_PWMSS_CLKCONFIG_EQEDCLK_EN 0x00000010
#define AM335X_PWMSS_CLKCONFIG_EQEDCLKSTOP_REQ 0x00000020
#define AM335X_PWMSS_REG_CLKSTATUS 0x00c
#define AM335X_PWMSS_REG_EPWM_TBCTL 0x200
#define AM335X_PWMSS_EPWM_TBCTL_CLKDIV_SET(x) ((x) << 10)
#define AM335X_PWMSS_EPWM_TBCTL_CLKDIV_MAX 7
#define AM335X_PWMSS_EPWM_TBCTL_SYNC0SEL_DIS 0x00000030
#define AM335X_PWMSS_EPWM_TBCTL_CTRMODE_UP 0x00000000
#define AM335X_PWMSS_EPWM_TBCTL_CTRMODE_DN 0x00000001
#define AM335X_PWMSS_EPWM_TBCTL_CTRMODE_UD 0x00000002
#define AM335X_PWMSS_EPWM_TBCTL_CTRMODE_SF 0x00000003
#define AM335X_PWMSS_REG_EPWM_TBSTS 0x202
#define AM335X_PWMSS_REG_EPWM_TBPHSHR 0x204
#define AM335X_PWMSS_REG_EPWM_TBPHS 0x206
#define AM335X_PWMSS_REG_EPWM_TBCNT 0x208
#define AM335X_PWMSS_REG_EPWM_TBPRD 0x20a
#define AM335X_PWMSS_EPWM_TBPRD_MAX 0xffff
#define AM335X_PWMSS_REG_EPWM_CMPCTL 0x20e
#define AM335X_PWMSS_REG_EPWM_CMPAHR 0x210
#define AM335X_PWMSS_REG_EPWM_CMPA 0x212
#define AM335X_PWMSS_REG_EPWM_CMPB 0x214
#define AM335X_PWMSS_REG_EPWM_AQCTLA 0x216
#define AM335X_PWMSS_REG_EPWM_AQCTLB 0x218
#define AM335X_PWMSS_EPWM_AQCTLA_CBD_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_CBD_CLR 0x0400
#define AM335X_PWMSS_EPWM_AQCTLA_CBD_SET 0x0800
#define AM335X_PWMSS_EPWM_AQCTLA_CBD_TGL 0x0c00
#define AM335X_PWMSS_EPWM_AQCTLA_CBU_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_CBU_CLR 0x0100
#define AM335X_PWMSS_EPWM_AQCTLA_CBU_SET 0x0200
#define AM335X_PWMSS_EPWM_AQCTLA_CBU_TGL 0x0300
#define AM335X_PWMSS_EPWM_AQCTLA_CAD_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_CAD_CLR 0x0040
#define AM335X_PWMSS_EPWM_AQCTLA_CAD_SET 0x0080
#define AM335X_PWMSS_EPWM_AQCTLA_CAD_TGL 0x00c0
#define AM335X_PWMSS_EPWM_AQCTLA_CAU_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_CAU_CLR 0x0010
#define AM335X_PWMSS_EPWM_AQCTLA_CAU_SET 0x0020
#define AM335X_PWMSS_EPWM_AQCTLA_CAU_TGL 0x0030
#define AM335X_PWMSS_EPWM_AQCTLA_PRD_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_PRD_CLR 0x0004
#define AM335X_PWMSS_EPWM_AQCTLA_PRD_SET 0x0008
#define AM335X_PWMSS_EPWM_AQCTLA_PRD_TGL 0x000c
#define AM335X_PWMSS_EPWM_AQCTLA_ZRO_NOP 0x0000
#define AM335X_PWMSS_EPWM_AQCTLA_ZRO_CLR 0x0001
#define AM335X_PWMSS_EPWM_AQCTLA_ZRO_SET 0x0002
#define AM335X_PWMSS_EPWM_AQCTLA_ZRO_TGL 0x0003
#define AM335X_PWMSS_REG_EPWM_AQSFRC 0x21a
#define AM335X_PWMSS_REG_EPWM_AQCSFRC 0x21c
#define AM335X_PWMSS_REG_EPWM_DBCTL 0x21e
#define AM335X_PWMSS_REG_EPWM_DBRED 0x220
#define AM335X_PWMSS_REG_EPWM_DBFED 0x222
#define AM335X_PWMSS_REG_EPWM_TZSEL 0x224
#define AM335X_PWMSS_REG_EPWM_TZCTL 0x228
#define AM335X_PWMSS_EPWM_TZCTL_TZA_NOP 0x00000003
#define AM335X_PWMSS_EPWM_TZCTL_TZB_NOP 0x0000000c
#define AM335X_PWMSS_REG_EPWM_TZEINT 0x22a
#define AM335X_PWMSS_REG_EPWM_TZFLG 0x22c
#define AM335X_PWMSS_REG_EPWM_TZCLR 0x22e
#define AM335X_PWMSS_REG_EPWM_TZFRC 0x230
#define AM335X_PWMSS_REG_EPWM_ETSEL 0x232
#define AM335X_PWMSS_REG_EPWM_ETPS 0x234
#define AM335X_PWMSS_REG_EPWM_ETFLG 0x236
#define AM335X_PWMSS_REG_EPWM_ETCLR 0x238
#define AM335X_PWMSS_REG_EPWM_ETFRC 0x23a
#define AM335X_PWMSS_REG_EPWM_PCCTL 0x23c
#define AM335X_PWMSS_REG_EPWM_HRCNFG 0x2c0
#define AM335X_PWMSS_REG_ECEP_QPOSCNT 0x180
#define AM335X_PWMSS_REG_ECEP_QPOSINIT 0x184
#define AM335X_PWMSS_REG_ECEP_QPOSMAX 0x188
#define AM335X_PWMSS_REG_ECEP_QPOSCMP 0x18c
#define AM335X_PWMSS_REG_ECEP_QPOSILAT 0x190
#define AM335X_PWMSS_REG_ECEP_QPOSSLAT 0x194
#define AM335X_PWMSS_REG_ECEP_QPOSLAT 0x198
#define AM335X_PWMSS_REG_ECEP_QUTMR 0x19c
#define AM335X_PWMSS_REG_ECEP_QUPRD 0x1a0
#define AM335X_PWMSS_REG_ECEP_QWDTMR 0x1a4
#define AM335X_PWMSS_REG_ECEP_QWDPRD 0x1a6
#define AM335X_PWMSS_REG_ECEP_QDECCTL 0x1a8
#define AM335X_PWMSS_REG_ECEP_QEPCTL 0x1aa
#define AM335X_PWMSS_REG_ECEP_QCAPCTL 0x1ac
#define AM335X_PWMSS_REG_ECEP_QPOSCTL 0x1ae
#define AM335X_PWMSS_REG_ECEP_QEINT 0x1b0
#define AM335X_PWMSS_REG_ECEP_QFLG 0x1b2
#define AM335X_PWMSS_REG_ECEP_QCLR 0x1b4
#define AM335X_PWMSS_REG_ECEP_QFRC 0x1b6
#define AM335X_PWMSS_REG_ECEP_QEPSTS 0x1b8
#define AM335X_PWMSS_REG_ECEP_QCTMR 0x1ba
#define AM335X_PWMSS_REG_ECEP_QCPRD 0x1bc
#define AM335X_PWMSS_REG_ECEP_QCTMRLAT 0x1be
#define AM335X_PWMSS_REG_ECEP_QCPRDLAT 0x1c0
#define AM335X_PWMSS_REG_ECEP_REVID 0x1dc
#define AM335X_PWMSS_ECEP_REVID 0x44d31103
#define AM335X_ADC_REG_REVISION 0x000
#define AM335X_ADC_REVISION_SCHEME_GET(x) (((x) & 0xc0000000) >> 30)
#define AM335X_ADC_REVISION_FUNC_GET(x) (((x) & 0x0fff0000) >> 16)
#define AM335X_ADC_REVISION_FUNC 0x730
#define AM335X_ADC_REVISION_X_MAJOR_GET(x) (((x) & 0x00000700) >> 8)
#define AM335X_ADC_REVISION_Y_MINOR_GET(x) (((x) & 0x0000001f) )
#define AM335X_ADC_REG_SYSCONFIG 0x010
#define AM335X_ADC_REG_IRQSTATUS_RAW 0x024
#define AM335X_ADC_REG_IRQSTATUS 0x028
#define AM335X_ADC_REG_IRQENABLE_SET 0x02c
#define AM335X_ADC_REG_IRQENABLE_CLR 0x030
#define AM335X_ADC_IRQENABLE_CLR_ALL 0xffffffff
#define AM335X_ADC_REG_IRQWAKEUP 0x034
#define AM335X_ADC_REG_DMAENABLE_SET 0x038
#define AM335X_ADC_REG_DMAENABLE_CLR 0x03c
#define AM335X_ADC_DMAENABLE_CLR_ALL 0x00000003
#define AM335X_ADC_REG_CTRL 0x040
#define AM335X_ADC_CTRL_SC_WP_N 0x00000004
#define AM335X_ADC_CTRL_SID 0x00000002
#define AM335X_ADC_CTRL_ENABLE 0x00000001
#define AM335X_ADC_REG_ADCSTAT 0x044
#define AM335X_ADC_REG_ADCRANGE 0x048
#define AM335X_ADC_REG_ADC_CLKDIV 0x04c
#define AM335X_ADC_REG_ADC_MISC 0x050
#define AM335X_ADC_REG_STEPENABLE 0x054
#define AM335X_ADC_STEPENABLE_STEP1 0x00000002
#define AM335X_ADC_STEPENABLE_STEP2 0x00000004
#define AM335X_ADC_STEPENABLE_STEP3 0x00000008
#define AM335X_ADC_STEPENABLE_STEP4 0x00000010
#define AM335X_ADC_STEPENABLE_STEP5 0x00000020
#define AM335X_ADC_STEPENABLE_STEP6 0x00000040
#define AM335X_ADC_STEPENABLE_STEP7 0x00000080
#define AM335X_ADC_STEPENABLE_STEP8 0x00000100
#define AM335X_ADC_REG_IDLECONFIG 0x058
#define AM335X_ADC_REG_TS_CHARGE_STEPCONFIG 0x05c
#define AM335X_ADC_REG_TS_CHARGE_DELAY 0x060
#define AM335X_ADC_REG_STEPCONFIG1 0x064
#define AM335X_ADC_REG_STEPDELAY1 0x068
#define AM335X_ADC_REG_STEPCONFIG2 0x06c
#define AM335X_ADC_REG_STEPDELAY2 0x070
#define AM335X_ADC_REG_STEPCONFIG3 0x074
#define AM335X_ADC_REG_STEPDELAY3 0x078
#define AM335X_ADC_REG_STEPCONFIG4 0x07c
#define AM335X_ADC_REG_STEPDELAY4 0x080
#define AM335X_ADC_REG_STEPCONFIG5 0x084
#define AM335X_ADC_REG_STEPDELAY5 0x088
#define AM335X_ADC_REG_STEPCONFIG6 0x08c
#define AM335X_ADC_REG_STEPDELAY6 0x090
#define AM335X_ADC_REG_STEPCONFIG7 0x094
#define AM335X_ADC_REG_STEPDELAY7 0x098
#define AM335X_ADC_REG_STEPCONFIG8 0x09c
#define AM335X_ADC_REG_STEPDELAY8 0x0a0
#define AM335X_ADC_REG_STEPCONFIG9 0x0a4
#define AM335X_ADC_REG_STEPDELAY9 0x0a8
#define AM335X_ADC_REG_STEPCONFIG10 0x0ac
#define AM335X_ADC_REG_STEPDELAY10 0x0b0
#define AM335X_ADC_REG_STEPCONFIG11 0x0b4
#define AM335X_ADC_REG_STEPDELAY11 0x0b8
#define AM335X_ADC_REG_STEPCONFIG12 0x0bc
#define AM335X_ADC_REG_STEPDELAY12 0x0c0
#define AM335X_ADC_REG_STEPCONFIG13 0x0c4
#define AM335X_ADC_REG_STEPDELAY13 0x0c8
#define AM335X_ADC_REG_STEPCONFIG14 0x0cc
#define AM335X_ADC_REG_STEPDELAY14 0x0d0
#define AM335X_ADC_REG_STEPCONFIG15 0x0d4
#define AM335X_ADC_REG_STEPDELAY15 0x0d8
#define AM335X_ADC_REG_STEPCONFIG16 0x0dc
#define AM335X_ADC_REG_STEPDELAY16 0x0e0
#define AM335X_ADC_STEPCONFIG_SEL_RFM_SET(x) ((x) << 23)
#define AM335X_ADC_STEPCONFIG_SEL_RFP_SET(x) ((x) << 12)
#define AM335X_ADC_STEPCONFIG_SEL_INP_SET(x) ((x) << 19)
#define AM335X_ADC_STEPCONFIG_SEL_INM_SET(x) ((x) << 15)
#define AM335X_ADC_STEPCONFIG_AVERAGE_1 0x00000000
#define AM335X_ADC_STEPCONFIG_AVERAGE_2 0x00000004
#define AM335X_ADC_STEPCONFIG_AVERAGE_4 0x00000008
#define AM335X_ADC_STEPCONFIG_AVERAGE_8 0x0000000c
#define AM335X_ADC_STEPCONFIG_AVERAGE_16 0x00000010
#define AM335X_ADC_REG_FIFO0COUNT 0x0e4
#define AM335X_ADC_REG_FIFO0THRESHOLD 0x0e8
#define AM335X_ADC_REG_DMA0REQ 0x0ec
#define AM335X_ADC_REG_FIFO1COUNT 0x0f0
#define AM335X_ADC_REG_FIFO1THRESHOLD 0x0f4
#define AM335X_ADC_REG_DMA1REQ 0x0f8
#define AM335X_ADC_REG_FIFO0DATA 0x100
#define AM335X_ADC_REG_FIFO1DATA 0x200
#define AM335X_ADC_FIFODATA_ID_GET(x) (((x) & 0x000f0000) >> 16)
#define AM335X_ADC_FIFODATA_DATA_GET(x) ((x) & 0x00000fff)
#define AM335X_ADC_FACTOR (1.8/4096.0)
#define AM335X_GPIO0_BASE 0x44e07000
#define AM335X_GPIO1_BASE 0x4804c000
#define AM335X_GPIO2_BASE 0x481ac000
#define AM335X_GPIO3_BASE 0x481ae000
#define AM335X_GPIO_SIZE 0x00001000
#define AM335X_GPIO_REG_REVISION 0x000
#define AM335X_GPIO_REVISION_FUNC_GET(x) (((x) & 0x0fff0000) >> 16)
#define AM335X_GPIO_REVISION_FUNC 0x060
#define AM335X_GPIO_REVISION_X_MAJOR_GET(x) (((x) & 0x00000700) >> 8)
#define AM335X_GPIO_REVISION_Y_MINOR_GET(x) (((x) & 0x0000003f) )
#define AM335X_GPIO_REG_SYSCONF 0x010
#define AM335X_GPIO_REG_EOI 0x020
#define AM335X_GPIO_REG_IRQSTATUS_RAW_0 0x024
#define AM335X_GPIO_REG_IRQSTATUS_RAW_1 0x028
#define AM335X_GPIO_REG_IRQSTATUS_0 0x02c
#define AM335X_GPIO_REG_IRQSTATUS_1 0x030
#define AM335X_GPIO_REG_IRQSTATUS_SET_0 0x034
#define AM335X_GPIO_REG_IRQSTATUS_SET_1 0x038
#define AM335X_GPIO_REG_IRQSTATUS_CLR_0 0x03c
#define AM335X_GPIO_REG_IRQSTATUS_CLR_1 0x040
#define AM335X_GPIO_REG_IRQWAKEN_0 0x044
#define AM335X_GPIO_REG_IRQWAKEN_1 0x048
#define AM335X_GPIO_REG_SYSSTATUS 0x114
#define AM335X_GPIO_REG_CTRL 0x130
#define AM335X_GPIO_REG_OE 0x134
#define AM335X_GPIO_REG_DATAIN 0x138
#define AM335X_GPIO_REG_DATAOUT 0x13c
#define AM335X_GPIO_REG_LEVELDETECT0 0x140
#define AM335X_GPIO_REG_LEVELDETECT1 0x144
#define AM335X_GPIO_REG_RISINGDETECT 0x148
#define AM335X_GPIO_REG_FALLINGDETECT 0x14c
#define AM335X_GPIO_REG_DEBOUNCENABLE 0x150
#define AM335X_GPIO_REG_DEBOUNCINGTIME 0x154
#define AM335X_GPIO_REG_CLEARDATAOUT 0x190
#define AM335X_GPIO_REG_SETDATAOUT 0x194
static inline uint32_t am335x_read32(void *base, size_t reg_offset)
{
volatile uint32_t *reg = (uint32_t *)((char *)base + reg_offset);
return *reg;
}
static inline void am335x_write32(void *base, size_t reg_offset, uint32_t value)
{
volatile uint32_t *reg = (uint32_t *)((char *)base + reg_offset);
*reg = value;
}
static inline uint16_t am335x_read16(void *base, size_t reg_offset)
{
volatile uint16_t *reg = (uint16_t *)((char *)base + reg_offset);
return *reg;
}
static inline void am335x_write16(void *base, size_t reg_offset, uint16_t value)
{
volatile uint16_t *reg = (uint16_t *)((char *)base + reg_offset);
*reg = value;
}
static inline uint8_t am335x_read8(void *base, size_t reg_offset)
{
volatile uint8_t *reg = (uint8_t *)((char *)base + reg_offset);
return *reg;
}
static inline void am335x_write8(void *base, size_t reg_offset, uint8_t value)
{
volatile uint8_t *reg = (uint8_t *)((char *)base + reg_offset);
*reg = value;
}
void *am335x_mem(size_t base, size_t size);
int am335x_cm_enable(size_t cm_off);
int am335x_pinmux_set(size_t offset, unsigned mode, unsigned flags);
int am335x_pinmux_gpio_offset(int gpio, int pin, size_t *offset);
int am335x_control_module_set(size_t offset, uint32_t bits);
#endif /* _INCLUDE_AM335X_ */