Maze X fdd1802bd5 Restructure CI pipeline for proper sequencing and parallelization ...

- Merge lint and test into single 'verify' job for guaranteed sequential execution
- Build job runs in parallel for each target, but waits for verify to complete
- Ensures order: verify (lint → test) → build (parallel) → publish-packages
- Fixes Gitea Actions job dependency handling

2026-03-27 18:08:42 +01:00

.gitea/workflows

Restructure CI pipeline for proper sequencing and parallelization

2026-03-27 18:08:42 +01:00

boards

Add custom board definition for Heltec WiFi LoRa 32 V3

2026-03-27 18:05:21 +01:00

hardware

Implement SX126X SPI and chip configuration for PoC

2026-03-27 17:33:23 +01:00

soc

Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton

2026-03-27 17:15:30 +01:00

src

Apply clang-format to source files and fix linter config

2026-03-27 17:48:39 +01:00

test

Add Python KISS client and integration test framework

2026-03-27 17:46:33 +01:00

.clang-format

Apply clang-format to source files and fix linter config

2026-03-27 17:48:39 +01:00

.clang-tidy

Add clang-format and clang-tidy to pre-commit hooks

2026-03-27 17:41:27 +01:00

.gitignore

Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton

2026-03-27 17:15:30 +01:00

.markdownlintrc.json

Initial setup

2026-03-27 16:46:56 +01:00

.pre-commit-config.yaml

Apply clang-format to source files and fix linter config

2026-03-27 17:48:39 +01:00

CI_CD.md

Add Gitea Actions CI/CD infrastructure with build matrix

2026-03-27 17:53:08 +01:00

platformio.ini

Add custom board definition for Heltec WiFi LoRa 32 V3

2026-03-27 18:05:21 +01:00

PROJECT.md

Scaffold PlatformIO project with 20 board configs and C99/C++ source skeleton

2026-03-27 17:15:30 +01:00

Description

LoRa KISS modem

87 KiB

Languages

C++ 54.4%

Python 37.3%

C 8.3%