maze
45d1364a71
- boards/seeed/xiao_wio_sx1262: add overlay, .conf, board.yml - app: support full set of SX12xx bandwidths; default BW set to 62 (62.5 kHz) - Update Kconfig and prj.conf - Update lora_modem.h/c for validation and mapping
20 lines
947 B
Plaintext
20 lines
947 B
Plaintext
# WARNING. THIS FILE IS AUTO-GENERATED. DO NOT MODIFY!
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#
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# This file contains build system settings derived from your modules.
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#
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# Modules may be set via ZEPHYR_MODULES, ZEPHYR_EXTRA_MODULES,
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# and/or the west manifest file.
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#
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# See the Modules guide for more information.
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/adi"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/ambiq"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/atmel"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/bouffalolab"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/espressif"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/gigadevice"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/microchip"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/nuvoton"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/nxp"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/stm32"
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"DTS_ROOT":"/Users/wijnand/zephyrproject/modules/hal/ti"
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